Engineering topics
Publications and source records attributed to Woo, D. S..
28 page report describes experiments in fabrication of integrated circuits with double-layer metalization. Double-layer metalization requires much less silicon "real estate" and allows more flexibility in placement of circuit elements than does single-layer metalization.
The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.
Conducting layer prevents static charges from accumulating during implantation of silicon-on-sapphire MOS structures. Either thick conducting film or thinner film transparent to ions is deposited prior to implantation, and gaps are etched in regions to be doped. Grounding path eliminates charge flow that damages film or cracks sapphire wafer. Prevention of charge buildup by simultaneously exposing structure to opposite charges requires equipment modifications less practical and more expensive than deposition of conducting layer.
The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.
Simpler than diffusion fabrication, ion bombardment produces complementary-metal-oxide-semiconductor / silicon-on-sapphire (CMOS/SOS) circuits that are one-third faster. Ion implantation simplifies the integrated circuit fabrication procedure and produces circuits with uniform characteristics.
Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.
Program is used to create complex lines, shapes, circles and alpha-numeric characters rapidly and easily, and format them for use on some pattern generation. System is applicable as aid to designers of microelectronics, integrated optics, bubble memories and other devices requiring precise artwork.
Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.
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Ultrasonic attenuation of alkali halide crystals in 120 to 180 degrees K range, noting thermal annealing of dislocation pinning centers