NASA NTRS · 19850030436
The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm
Abstract
Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes often requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.
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Hsu, I.-S., Reed, I. S., Wang, K., Yeh, C.-S., Truong, T. K., Deutsch, L. J.. 1984-10-01. The VLSI implementation of a Reed-Solomon encoder using Berlekamp's bit-serial multiplier algorithm. https://ntrs.nasa.gov/citations/19850030436
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