Search NASA⌕ Search
Home/Archive/NASA NTRS

NASA NTRS · 20060051815

Delta Doping High Purity CCDs and CMOS for LSST

Blacksberg, Jordana·Nikzad, Shouleh·Hoenk, Michael·Elliott, S. Tom·Bebek, Chris·Holland, Steve·Kolbe, Bill
View original source ↗Export metadata ↓

Abstract

A viewgraph presentation describing delta doping high purity CCD's and CMOS for LSST is shown. The topics include: 1) Overview of JPL s versatile back-surface process for CCDs and CMOS; 2) Application to SNAP and ORION missions; 3) Delta doping as a back-surface electrode for fully depleted LBNL CCDs; 4) Delta doping high purity CCDs for SNAP and ORION; 5) JPL CMP thinning process development; and 6) Antireflection coating process development.

Explore related subjects

CMOSDelta dopingCCDdetectors

Keep this discovery

Explore connections, maps & timelines

BibTeXRIS

Blacksberg, Jordana, Nikzad, Shouleh, Hoenk, Michael, Elliott, S. Tom, Bebek, Chris, Holland, Steve, Kolbe, Bill. 2006-01-01. Delta Doping High Purity CCDs and CMOS for LSST. https://ntrs.nasa.gov/citations/20060051815

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related reports

DOE OSTI2025

Multistate resistance in TaN/(Hf,Zr)O 2 /Ta ferroelectric tunnel junctions

Ferroelectric tunnel junctions (FTJs) utilizing hafnium zirconium oxide (HZO) have emerged as promising non-volatile memory elements for microelectronics, compatible with back end of line (BEOL) complementary–metal–oxide semiconductor fabrication. This study investigates asymmetric electrode TaN/HZO/Ta devices with a 6 nm thick HZO layer as FTJs for multistate resistive memory applications. The individual FTJs exhibit a resistance ratio exceeding 10× when utilized as a binary state device, with pulsing between −1.7 and +1.4 V to set the high resistance state (HRS) and low resistance state (LRS), respectively. Following with reduced write voltage pulses allows the ferroelectric device to operate with a selection of over 32 distinct resistance states (2 5 bits) between the LRS and HRS. This work then explores the stability of the resistance states during write/read pulse cycling, along with the stability of the state after multiple read pulses. Accessing the multibit state shows stability within 50 reads with the binary state remaining stable for more than 4000 reads pulses. With their multistate tunability and versatility, FTJs hold promise as BEOL memory elements for compute-in-memory (CiM) arrays, binary digital memory, or weighted vector matrix multiplication applications with low power consumption during computations.

CMOS↗