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Resistor Extends Life Of Battery In Clocked CMOS Circuit

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Wells, George H., Jr.

The Impact of Bias Row Noise to Photometric Accuracy: Case Study Based on a Scientific CMOS Detector

Abstract We tested a new model of CMOS detector manufactured by the Gpixel Inc, for potential space astronomical application. In laboratory, we obtain some bias images under the typical application environment. In these bias images, clear random row noise pattern is observed. The row noise also contains some characteristic spatial frequencies. We quantitatively estimated the impact of this feature to photometric measurements, by making simulated images. We compared different bias noise types under strict parameter control. The result shows the row noise will significantly deteriorate the photometric accuracy. It effectively increases the readout noise by a factor of 2–10. However, if it is properly removed, the image quality and photometric accuracy will be significantly improved.

Astronomy & Astrophysics

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

Quinn, Adam [Fermilab] (ORCID:0009000605056371)

Reconfigurable Cascaded Thermal Neuristors for Neuromorphic Computing

While the complementary metal-oxide semiconductor (CMOS) technology is the mainstream for the hardware implementation of neural networks, an alternative route is explored based on a new class of spiking oscillators called “thermal neuristors”, which operate and interact solely via thermal processes. Utilizing the insulator-to-metal transition (IMT) in vanadium dioxide, a wide variety of reconfigurable electrical dynamics mirroring biological neurons is demonstrated. Notably, inhibitory functionality is achieved just in a single oxide device, and cascaded information flow is realized exclusively through thermal interactions. To elucidate the underlying mechanisms of the neuristors, a detailed theoretical model is developed, which accurately reflects the experimental results. In conclusion, this study establishes the foundation for scalable and energy-efficient thermal neural networks, fostering progress in brain-inspired computing.

36 MATERIALS SCIENCE

Temperature-Dependent Transport Characteristics of 2D MoS2 Channel FETs Grown Using Salt-Based Precursors

D Transition Metal Dichalcogenides (TMDs), particularly MoS2, are promising candidates for sub-10 nm Gate All Around (GAA) CMOS FETs. Salt-assisted Chemical Vapor Deposition (CVD) enable lateral MoS2 growth at atmospheric pressure and low temperatures. This work analyzes salt-based precursor-driven CVD-grown MoS2 FETs at various temperatures. MoS2 was grown using Ammonium Molybdate salt, sulfurized at 750∘C, and transferred onto p−Si3/SiO2 substrates. At room temperature, threshold voltage (VT) ranged from -35 V to -25 V, with a peak drain current of 1.2μA/μm. As temperature increased above 325K, VT shifted exponentially, and carrier mobility dropped significantly. At 400 K, the gate lost channel control, though gate leakage current remained low. These results are compared with non-salt-based MoS2 growth to assess salt precursor effects.Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (https://www.energy.gov/doe-public-access-plan).

Jones, Andrew [ORNL] (ORCID:0009000233849687)

Machine learning pipeline for denoising low signal-to-noise ratio and out-of-distribution transmission electron microscopy datasets

High-resolution transmission electron microscopy (HRTEM) is crucial for observing material’s structural and morphological evolution at Angstrom scales, but the electron beam can alter these processes. Devices such as CMOS-based direct-electron detectors operating in electron-counting mode can be utilized to substantially reduce the electron dosage. However, the resulting images often lead to a low signal-to-noise ratio, which requires frame integration that sacrifices temporal resolution. Several machine learning (ML) models have been recently developed to successfully denoise HRTEM images. Yet, these models are often computationally expensive, and their inference speeds on GPUs are outpaced by the imaging speed of advanced detectors, precluding in situ analysis. Furthermore, the performance of these denoising models on datasets with imaging conditions that deviate from the training datasets has not been evaluated. To mitigate these gaps, we propose a new self-supervised ML denoising pipeline specifically designed for time-series HRTEM images. This pipeline integrates a blind-spot convolution neural network with pre-processing and post-processing steps, including drift correction and low-pass filtering. Results demonstrate that our model outperforms various other ML and non-ML denoising methods in noise reduction and contrast enhancement, leading to improved visual clarity of atomic features. Additionally, the model is drastically faster than U-Net-based ML models and demonstrates excellent out-of-distribution generalization. The model’s computational inference speed is in the order of milliseconds per image, rendering it suitable for application in in-situ HRTEM experiments.

36 MATERIALS SCIENCE

Evaluation of 3D pixel silicon sensors for the CMS Phase-2 Inner Tracker

The high-luminosity upgrade of the CERN LHC requires the replacement of the CMS tracking detector to cope with the increased radiation fluence while maintaining its excellent performance. An extensive R&D program, aiming at using 3D pixel silicon sensors in the innermost barrel layer of the detector, has been carried out by CMS in collaboration with the FBK (Trento, Italy) and CNM (Barcelona, Spain) foundries. The sensors will feature a pixel cell size of 25 × 100 µm 2 , with a centrally located electrode connected to the readout chip. The sensors are read out by the RD53A and CROCv1 chips, developed in 65 nm CMOS technology by the RD53 Collaboration, a joint effort between the ATLAS and CMS groups. This paper reports the results achieved in beam test experiments before and after irradiation, up to a fluence of approximately 2 . 6 × 1 0 16 n eq /cm 2 . Measurements of assemblies irradiated to a fluence of 1 × 10 16 n˙eq/cm 2 show a hit detection efficiency higher than 96% at normal incidence, with fewer than 2% of channels masked, across a bias voltage range greater than 50 V . Even after irradiation to a higher fluence of 1.6 × 10 16 n˙eq/cm 2 , similar performance is maintained over a bias voltage range of 30 V , remaining well within CMS requirements.

3D pixel