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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Enhanced Low Dose Rate Effects in Bipolar Circuits: A New Hardness Assurance Problem for NASA

Many bipolar integrated circuits are much more susceptible to ionizing radiation at low dose rates than they are at high dose rates typically used for radiation parts testing. Since the low dose rate is equivalent to that seen in space, the standard lab test no longer can be considered conservative and has caused the Air Force to issue an alert. Although a reliable radiation hardness assurance test has not yet been designed, possible mechanisms for low dose rate enhancement and hardness assurance tests are discussed.

bipolar integrated circuits↗
NASA NTRS2018

Sixty Earth-Days Test of a Prototype Pt/HTCC Alumina Package in Simulated Venus Environment

This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degrees Centigrade Earth air ambient for over ten thousand hours, and short-term tested at temperatures above 800 degrees Centigrade. The three-phase harsh environment test started with 48 hours in 465 degrees Centigrade Earth air, followed by 48 hours in 465 degrees Centigrade nitrogen at 90-bar pressure and 1400 hours in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars. Initial analytical results of the package materials and surfaces after exposure to the Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in a simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.

Chen, Liang-Yu↗
DOE OSTI2022

Real-Time Seismic System for Monitoring, Imaging, and Characterization (RT-SEISMIC)

The goal of this Laboratory Directed Research and Development (LDRD) project was to develop a borehole seismic source and sensor array to enable real-time seismic imaging at scales and conditions relevant to the energy industry including both fossil-energy and geothermal. In FY21 and FY22, we designed, built, and tested both a prototype impulse source module for generating seismic energy and a sensing module for recording ground motions generated by the source module array. A pneumatically driven vibratory source was also designed. The source modules were fabricated with all high temperature components and the team has worked to incorporate the current RT-SEISMIC electronics design into a commercially available, high temperature silicon-on-insulator chip integrated circuit. Several issues were identified during fabrication and lab testing that led to redesign of several system components and subsequent retesting. The final round of testing showed that while metal/graphite-based seals worked quite well for static seals, they were unable to provide an adequate gas seal for dynamic, reciprocating part movements which necessitated a final redesign using Kalrez. This change will result in a continuous temperature rating of approximately 275 degrees C for the system. While a field test of the RT-SEISMIC system was targeted in FY22, due to the extended lab testing and redesign efforts, field testing was not achieved. As a result of this LDRD investment, several sponsors have expressed interest in RT-SEISMIC and we expect to continue towards a field demonstration of the full system in the future.

58 GEOSCIENCES↗
DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Time-Sensitive Quantum Key Distribution (TSQKD)

This is the final report for the Time-Sensitive Quantum Key Distribution (TSQKD) project and summarizes the demonstration and longer-term field testing at an electric utility, EPB of Chattanooga, in Chattanooga, TN. The demonstration was held virtually (due to the COVID pandemic) and successfully executed the tests outlined in a prior report, “Task 10: Develop a QKD Time-Sensitive Networking Test Suite” submitted 9/30/2020. The portable test equipment explained in Task 10 and earlier task reports was tested at GE Research remotely connected with Qubitekk’s QKD equipment in San Diego, CA. Then the equipment was shipped to Qubitekk for physical integration with Qubitekk’s Quantum DataLoc™ Key Server 1570nm (http://qubitekk.com/products/qkd-for-industrial-control-systems-ics/). The portable test equipment was shipped from Qubitekk to EPB for demonstration and extended field testing. A summary of the demonstration and test results are described in this report. The demo and extended field test results are enabled by the NETCONF/YANG IEEE P1913 data management model developed as part of this project (Task 5). The NETCONF/YANG IEEE P1913 data management model demonstrated significant practical utility in providing a common means of monitoring and configuring the QKD system. All data in this report comes from the IEEE P1913 data management model.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1971

Development and performance of pulse-width-modulated static inverter and converter modules

Pulse-width-modulated inverter and converter modules are being developed for modular aerospace electrical power systems. The modules, rate 2.5 kilowatts per module and 10-minute - 150-percent overload, operate from 56 volts dc. The converter module provides two output voltages: a nominal link voltage of 200 volts dc when used with the inverter, and 150 volts dc to a load bus when used separately. The inverter module output is 400-hertz, sinusoidal, three-phase, 120/208 volts. Tests of breadboard models with standard parts and integrated circuits show rated power efficiencies of 71.4 and 85.1 percent and voltage regulation of 5 and 3.1 percent for inverter and converter modules, respectively. Sine-wave output distortion is 0.74 percent.

Pittman, P. F.↗
NASA NTRS1985

Fault models

A major problem in the qualification of integrated circuit cells and in the development of adequate tests for the circuits is to lack of information on the nature and density of fault models. Some of this information is being obtained from the test structures. In particular, the Pinhole Array Capacitor is providing values for the resistance of gate oxide shorts, and the Addressable Inverter Matrix is providing values for parameter distributions such as noise margins. Another CMOS fault mode, that of the open-gated transistor, is examined and the state of the transistors assessed. Preliminary results are described for a number of open-gated structures such as transistors, inverters, and NAND gates. Resistor faults are applied to various CMOS gates and the time responses are noted. The critical value for the resistive short to upset the gate response was determined.

Sayah, H. R.↗
NASA NTRS1992

More About Vector Adaptive/Predictive Coding Of Speech

Report presents additional information about digital speech-encoding and -decoding system described in "Vector Adaptive/Predictive Encoding of Speech" (NPO-17230). Summarizes development of vector adaptive/predictive coding (VAPC) system and describes basic functions of algorithm. Describes refinements introduced enabling receiver to cope with errors. VAPC algorithm implemented in integrated-circuit coding/decoding processors (codecs). VAPC and other codecs tested under variety of operating conditions. Tests designed to reveal effects of various background quiet and noisy environments and of poor telephone equipment. VAPC found competitive with and, in some respects, superior to other 4.8-kb/s codecs and other codecs of similar complexity.

Jedrey, Thomas C.↗
NASA NTRS2000

Integrated Circuit Immunity

This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

Sketoe, J. G.↗
NASA NTRS1990

Support system for a 1750A VHSIC multiprocessor

A design approach for a support system or test station necessary to functionally operate a very high-speed integrated circuit (VHSIC) microprocessor brassboard is presented. Major subsystems which make up the support are the following: (1) power supply unit; (2) temperature controller unit; (3) input/output module; and (4) mechanical test fixture. Theoretical analyses and experimental techniques were utilized to design and implement the power and temperature requirements for the VHSIC processor. A functional description of the input/output module and test fixture is discussed. The support system provides the means to evaluate and functionally test a VHSIC microprocessor.

Ruggles, Stephen L.↗
NASA NTRS1994

Versatile Dual-Channel Waveform Generator

Programmable waveform generator synthesizes two independent waveforms simultaneously at frequencies up to 250 MHz. Can be in phase or out of phase with each other. Use of commercial integrated circuits helps keep cost low. Operation governed by BASIC source code enabling any user equipped with suitable personal computer to specify waveforms. User can modify source code to satisfy special needs. Other applications include simulation of Doppler waveforms for radar, and of video signals for testing color displays and computer monitors. With eventual substitution of gallium arsenide integrated circuits for its present silicon integrated circuits, instrument able to generate waveforms with 14-bit precision and sample rates as high as 2 GHz.

Staples, Edward J.↗
NASA NTRS2006

NASA Tech Briefs, March 2006

Topics covered include: Medical Signal-Conditioning and Data-Interface System; Instruments for Reading Direct-Marked Data-Matrix Symbols; Processing EOS MLS Level-2 Data; Ground Processing of Data From the Mars Exploration Rovers; Estimating Total Electron Content Using 1,000+ GPS Receivers; NASA Solar Array Demonstrates Commercial Potential; Improved Control of Charging Voltage for Li-Ion Battery; Programmable Pulse-Position-Modulation Encoder; Wavelength-Agile External-Cavity Diode Laser for DWDM; Pattern-Recognition Processor Using Holographic Photopolymer; Submicrosecond Power-Switching Test Circuit; Three-Function Logic Gate Controlled by Analog Voltage; Integrated System for Autonomous Science; Montage Version 3.0; Utilizing AI in Temporal, Spatial, and Resource Scheduling; Satellite Image Mosaic Engine; Architecture for Control of the K9 Rover; HFGMC Enhancement of MAC/GMC; Automated Activation and Deactivation of a System Under Test; Cleaning Carbon Nanotubes by Use of Mild Oxygen Plasmas; Generating Aromatics From CO2 on Mars or Natural Gas on Earth; Attaching Thermocouples by Peening or Crimping; Heat Treatment of Friction-Stir-Welded 7050 Aluminum Plates; Generating Breathable Air Through Dissociation of N2O; High-Performance Scanning Acousto-Ultrasonic System; Correction for Thermal EMFs in Thermocouple Feedthroughs; Using Quasiparticle Poisoning To Detect Photons; Estimating Resolution Lengths of Hybrid Turbulence Models; Education and Training Module in Alertness Management; Cargo-Positioning System for Next-Generation Spacecraft; Micro-Imagers for Spaceborne Cell-Growth Experiments; Holographic Solar Photon Thrusters; Plasma-Based Detector of Outer-Space Dust Particles; and Generation of Data-Rate Profiles of Ka-Band Deep-Space Links.

Source record↗
NASA NTRS2013

Small Radioisotope Power System Testing at NASA Glenn Research Center

In April 2009, NASA Glenn Research Center (GRC) formed an integrated product team (IPT) to develop a Small Radioisotope Power System (SRPS) utilizing a single Advanced Stirling Convertor (ASC) with passive balancer. A single ASC produces approximately 80 We making this system advantageous for small distributed lunar science stations. The IPT consists of Sunpower, Inc., to provide the single ASC with a passive balancer, The Johns Hopkins University Applied Physics Laboratory (JHUAPL) to design an engineering model Single Convertor Controller (SCC) for an ASC with a passive balancer, and NASA GRC to provide technical support to these tasks and to develop a simulated lunar lander test stand. The single ASC with a passive balancer, simulated lunar lander test stand, and SCC were delivered to GRC and were tested as a system. The testing sequence at GRC included SCC fault tolerance, integration, electromagnetic interference (EMI), vibration, and extended operation testing. The SCC fault tolerance test characterized the SCCs ability to handle various fault conditions, including high or low bus power consumption, total open load or short circuit, and replacing a failed SCC card while the backup maintains control of the ASC. The integrated test characterized the behavior of the system across a range of operating conditions, including variations in cold-end temperature and piston amplitude, including the emitted vibration to both the sensors on the lunar lander and the lunar surface. The EMI test characterized the AC and DC magnetic and electric fields emitted by the SCC and single ASC. The vibration test confirms the SCCs ability to control the single ASC during launch. The extended operation test allows data to be collected over a period of thousands of hours to obtain long term performance data of the ASC with a passive balancer and the SCC. This paper will discuss the results of each of these tests.

Vibration↗
NASA NTRS1982

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Woo, D. S.↗
NASA NTRS1993

X-Ray-Diffraction Tests Of Irradiated Electronic Devices: II

Report describes research on use of x-ray diffraction to measure stresses in metal conductors of complementary metal oxide/semiconductor (CMOS) integrated circuits exposed to ionizing radiation. Expanding upon report summarized in "X-Ray-Diffraction Tests Of Irradiated Electronic Devices: I" (NPO-18803), presenting data further suggesting relationship between electrical performances of circuits and stresses and strains in metal conductors.

Shaw, David C.↗
NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗
NASA NTRS1988

Development of gallium arsenide high-speed, low-power serial parallel interface modules: Executive summary

Final report to NASA LeRC on the development of gallium arsenide (GaAS) high-speed, low power serial/parallel interface modules. The report discusses the development and test of a family of 16, 32 and 64 bit parallel to serial and serial to parallel integrated circuits using a self aligned gate MESFET technology developed at the Honeywell Sensors and Signal Processing Laboratory. Lab testing demonstrated 1.3 GHz clock rates at a power of 300 mW. This work was accomplished under contract number NAS3-24676.

Source record↗
NASA NTRS1983

Practical preventive reliability using matrix forms

This paper describes a practical new tool to improve the reliability of equipment. It uses a matrix form to help monitor anticipated component faults precisely. The tool provides the practical measures necessary to generate matrix tables that accurately display all causes of failure and all planned programmatic analyses, tests, processes, and inspections. When completed, the matrix tables give users in-depth visibility of the degree of protection against component failure that is provided by the program's preventive measure plans. The matrix form is an excellent technique for tracking, and thereby influencing, the reliability of nonelectronic spacecraft subsystems or components. No electronic applications have been tried, but the procedure can be useful in the electronics field, e.g., in integrated circuit production planning, and perhaps in process control, inspection or test lines for other electronic components. The drawing of forms, and the recording/manipulation of the data can be computerized.

Johnson, S. A.↗