MOS field-effect-transistor technology
Metal oxide semiconductor field effect transistor circuit development and laminated electronic packaging for computer storage devices
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Metal oxide semiconductor field effect transistor circuit development and laminated electronic packaging for computer storage devices
Positive ion current emission by tungsten and molybdenum studied for influence of impurities on MOSFET transistors
Second breakdown of transistors with diffused emitter, epitaxial collector and base, obtaining maximum operating current dependence on base width and resistivity
Power transistor reliability against second breakdown, locating breakdown by IR fast scan microscope and measuring breakdown voltage
Nonlinear theory of class of transistor oscillators using Ebers-Moll large signal model and differential equation
High capacity random access magnetic memory storage device combining integrated array of MOS transistors and laminated ferrite memory planes
Test equipment for second breakdown characteristics of power transistors
Power transistor second breakdown failures, discussing reliability improvement
Counting rate meter compresses a wide range of data values, or decades of current. Silicon planar transistor, operating in the zero collector-base voltage mode, is used as a feedback element in an operational amplifier to obtain the log response.
Two techniques have been conceptually proposed as possible means of reducing parasitic beta in lateral p-n-p transistors. One method uses a degenerate substrate and high concentration P /plus/ guard-ring diffusion, another places the base contact at the center of an annular ring structure.
Metal-Insulated-Semiconductor Field Effect Transistor /MISFET/ device uses a silicon nitride passivation layer over a thin silicon oxide layer to enhance the radiation tolerance. It is useful in electronic systems exposed to space radiation environment or the effects of nuclear weapons.
Fabrication process improves the size ratio and shape factor of the base region of self-isolating transistor arrays. Basic processing steps in the modified method include, sub-diffusion, epitaxial layer growth, isolation-diffusions, enhancement diffusions, aluminum interconnect deposition, and testing and packaging.
Fabrication technique produces field aided lateral PNP transistors compatible with micropower switching circuits. The sub-collector diffusion is performed with phosphorus as the dopant and the epitaxy is grown using the higher temperature silicon tetrachloride process.
Silicon nitride and cermet resistors for binary counter metal insulator field effect transistor circuit
Criteria applied to semiconductor materials and deposition processes for thick film, insulated gate field effect transistor fabrication
Statistical analysis of data obtained with 1 MeV tests on transistors
Radiation effects on silicon nitride insulated gate field effect transistors
Encapsulation technique for multiple chip silicon switching transistors with silver-Teflon contacts