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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

Radiation effects on microelectronics and future space missions

This paper briefly reviews the three basic radiation effect mechanisms, and how they interrupt the functionality of currently available non-volatile memory technologies. This paper also presents a very general overview of the radiation environments expected in future space exploration missions. Unfortunately, these environments will be very harsh, from a radiation standpoint, and thus a significant effort is required to develop non-volatile technologies that will meet future mission requirements.

radiation effects↗
NASA NTRS2007

CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

Yeh, Penshu↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At an earlier conference we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art CMOS technologies. In this presentation, we extend this discussion focusing on the following areas: (1) Device packaging, (2) Evolving physical single even upset mechanisms, (3) Device complexity, and (4) the goal of understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS2008

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

LaBel, Kenneth A.↗
NASA NTRS2003

A Monte Carlo Model for LET Spectra of 200 MeV Protons Used for Microelectronic Testing

The direct ionization Linear Energy Transfer (LET) for 200 MeV protons in silicon is much smaller than that for higher charged particles since LET increases as the square of the ion charge. However, occasionally the proton interacts with the silicon nuclei and produces a shower of fragments and a recoiling nucleus. When this happens, the LET produced is much greater than the direct ionization LET. Testing the single event effect susceptibility of components using energetic (200 MeV) protons is often the only viable option for system level testing commercial-off-the-shelf (COTS) avionics that have not been designed for space environments. However, the question of how a system tested with protons will perform in a heavy ion environment arises. Here the concern is not only with prediction of on-orbit upset rate, but also about possibility of on-orbit failures that were not observed during proton testing.

O'Neill, Patrick M.↗
NASA NTRS2018

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗
NASA NTRS2004

Pb-free microelectronics assembly in aerospace applications

In this paper we provide a snapshot of the commericial industry trends and how they may impact electronics in the aerospace environment. Impacts will be felt in the areas of: reliability, assembly methods, cost drivers, supply chain selection and alternate materials selection.

Schoenung, Julie M.↗
NASA NTRS2008

Vacuum microelectronics and miniature instruments based on application specific electrode-integrated nanotube cathodes (ASINCs)

JPL has developed high performance cold cathodes using arrays of carbon nanotube bundles thay routinely produce > 15 A/cm2 at 5 to 8 V/μm applied fields for extreme environment vacuum electronics and miniature instrumentation. These cathodes have been monolithically integrated with additional electrodes using double siliconon-insulator process.

Mojarradi, M.M.↗