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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16

THz semiconductor-based front-end receiver technology for space applications

Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

Schottky diode multipliers↗

Properties of a Variable-Delay Polarization Modulator

We investigate the polarization modulation properties of a variable-delay polarization modulator (VPM). The VPM modulates polarization via a variable separation between a polarizing grid and a parallel mirror. We find that in the limit where the wavelength is much larger than the diameter of the metal wires that comprise the grid, the phase delay derived from the geometric separation between the mirror and the grid is sufficient to characterize the device. However, outside of this range, additional parameters describing the polarizing grid geometry must be included to fully characterize the modulator response. In this paper, we report test results of a VPM at wavelengths of 350 micron and 3 mm. Electromagnetic simulations of wire grid polarizers were performed and are summarized using a simple circuit model that incorporates the loss and polarization properties of the device.

Chuss, David T.↗

Effect of Inductive Coil Geometry and Current Sheet Trajectory of a Conical Theta Pinch Pulsed Inductive Plasma Accelerator

Results are presented demonstrating the e ect of inductive coil geometry and current sheet trajectory on the exhaust velocity of propellant in conical theta pinch pulsed induc- tive plasma accelerators. The electromagnetic coupling between the inductive coil of the accelerator and a plasma current sheet is simulated, substituting a conical copper frustum for the plasma. The variation of system inductance as a function of plasma position is obtained by displacing the simulated current sheet from the coil while measuring the total inductance of the coil. Four coils of differing geometries were employed, and the total inductance of each coil was measured as a function of the axial displacement of two sep- arate copper frusta both having the same cone angle and length as the coil but with one compressed to a smaller size relative to the coil. The measured relationship between total coil inductance and current sheet position closes a dynamical circuit model that is used to calculate the resulting current sheet velocity for various coil and current sheet con gura- tions. The results of this model, which neglects the pinching contribution to thrust, radial propellant con nement, and plume divergence, indicate that in a conical theta pinch ge- ometry current sheet pinching is detrimental to thruster performance, reducing the kinetic energy of the exhausting propellant by up to 50% (at the upper bound for the parameter range of the study). The decrease in exhaust velocity was larger for coils and simulated current sheets of smaller half cone angles. An upper bound for the pinching contribution to thrust is estimated for typical operating parameters. Measurements of coil inductance for three di erent current sheet pinching conditions are used to estimate the magnetic pressure as a function of current sheet radial compression. The gas-dynamic contribution to axial acceleration is also estimated and shown to not compensate for the decrease in axial electromagnetic acceleration that accompanies the radial compression of the plasma in conical theta pinches.

Hallock, Ashley K.↗

Impulse Testing of Corporate-Fed Patch Array Antennas

This paper discusses a novel method for detecting faults in antenna arrays. The method, termed Impulse Testing, was developed for corporate-fed patch arrays where the element is fed by a probe and is shorted at its center. Impulse Testing was devised to supplement conventional microwave measurements in order to quickly verify antenna integrity. The technique relies on exciting each antenna element in turn with a fast pulse (or impulse) that propagates through the feed network to the output port of the antenna. The resulting impulse response is characteristic of the path through the feed network. Using an oscilloscope, a simple amplitude measurement can be made to detect faults. A circuit model of the antenna elements and feed network was constructed to assess various fault scenarios and determine fault-detection thresholds. The experimental setup and impulse measurements for two patch array antennas are presented. Advantages and limitations of the technique are discussed along with applications to other antenna array topologies

antenna array↗

Lunar Crater Mini-Wakes: Structure, Variability, and Volatiles

Within a permanently shadowed lunar crater the horizontal flow of solar wind is obstructed by upstream topography, forming a regional plasma mini-wake. In the present work kinetic simulations are utilized to investigate how the most prominent structural aspects of a crater mini-wake are modulated during passage of a solar storm. In addition, the simulated particle fluxes are coupled into an equivalent-circuit model of a roving astronaut,. including triboelectric charging due to frictional contact with the lunar regolith, to characterize charging of the astronaut suit during the various stages of the storm. In some cases, triboelectric charging of the astronaut suit becomes effectively perpetual, representing a critical engineering concern for roving within shadowed lunar regions. Finally, the present results suggest that wake structure plays a critical role in modulating the spatial distribution of volatiles at the lunar poles.

Zimmerman, Michael I.↗

Plasma Wake Simulations and Object Charging in a Shadowed Lunar Crater During a Solar Storm

Within a permanently shadowed lunar crater the horizontal flow of solar wind is obstructed by upstream topography, forming a plasma wake that electrostatically diverts ions toward the crater floor and generates a surface potential that can reach kilovolts. In the present work kinetic plasma simulations are employed to investigate the morphology of a lunar crater wake during passage of a solar storm. Results are cast in terms of leading dimensionless ratios including the ion Mach number, ratio of crater depth to plasma Debye length, peak secondary electron yield, and electron temperature vs. electron impact energy at peak secondary yield. This small set of ratios allows generalization to a much wider range of scenarios. The kinetic simulation results are fed forward into an equivalent-circuit model of a roving astronaut. In very low-plasma-current environments triboelectric charging of the astronaut suit becomes effectively perpetual, representing a critical engineering concern for roving within shadowed lunar regions. Finally, simulated ion fluxes are used to explore sputtering and implantation processes within an idealized crater. It is suggested that the physics of plasma mini-wakes formed in the vicinity of permanently shadowed topography may play a critical role in modulating the enigmatic spatial distribution of volatiles at the lunar poles.

Zimmerman, Michael I.↗

Experimental Investigation of a Direct-drive Hall Thruster and Solar Array System at Power Levels up to 10 kW

As NASA considers future exploration missions, high-power solar-electric propulsion (SEP) plays a prominent role in achieving many mission goals. Studies of high-power SEP systems (i.e. tens to hundreds of kilowatts) suggest that significant mass savings may be realized by implementing a direct-drive power system, so NASA recently established the National Direct-Drive Testbed to examine technical issues identified by previous investigations. The testbed includes a 12-kW solar array and power control station designed to power single and multiple Hall thrusters over a wide range of voltages and currents. In this paper, single Hall thruster operation directly from solar array output at discharge voltages of 200 to 450 V and discharge powers of 1 to 10 kW is reported. Hall thruster control and operation is shown to be simple and no different than for operation on conventional power supplies. Thruster and power system electrical oscillations were investigated over a large range of operating conditions and with different filter capacitances. Thruster oscillations were the same as for conventional power supplies, did not adversely affect solar array operation, and were independent of filter capacitance from 8 to 80 ?F. Solar array current and voltage oscillations were very small compared to their mean values and showed a modest dependence on capacitor size. No instabilities or anomalous behavior were observed in the thruster or power system at any operating condition investigated, including near and at the array peak power point. Thruster startup using the anode propellant flow as the power 'switch' was shown to be simple and reliable with system transients mitigated by the proper selection of filter capacitance size. Shutdown via cutoff of propellant flow was also demonstrated. A simple electrical circuit model was developed and is shown to have good agreement with the experimental data.

Snyder, John S.↗

Digital twin advanced distribution management systems (ADMS) and methods

Advanced Distribution Management Systems not generally optimize over the entire feeder because there are few high-fidelity distribution circuit models and real-time distribution-connected sensors are rare. The limited observability at the distribution level makes it difficult to globally optimize distribution operations and issue control setpoints to power systems equipment or Distributed Energy Resources (DER) to perform grid-support services. For example, setpoints can be issued to DER based on results from an optimization module that incorporates a static or time-series feeder simulation. Feeder simulation initial conditions are populated with photovoltaic (PV) and load forecasts, state estimation results, and/or digital twin measurements or state output. The real-time (RT) digital twin runs a model of the feeder to generate state estimation pseudo-measurements since there are limited live feeder measurements.

Johnson, Jay Tillay↗

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗

Opportunities and Challenges of Computational Electromagnetics Methods for Superconducting Circuit Quantum Device Modeling: A Practical Review

High-fidelity numerical methods that model the physical layout of a device are essential for the design of many technologies. For methods that characterize electromagnetic effects, these numerical methods are referred to as computational electromagnetics (CEM) methods. Although the CEM research field is mature, emerging applications can still stress the capabilities of the techniques in use today. The design of superconducting circuit quantum devices falls in this category due to the unconventional material properties and important features of the devices covering nanometer to centimeter scales. Such multiscale devices can stress the fundamental properties of CEM tools which can lead to an increase in simulation times, a loss in accuracy, or even cause no solution to be reliably found. While these challenges are being investigated by CEM researchers, knowledge about them is limited in the broader community of users of these CEM tools. This review is meant to serve as a practical introduction to the fundamental aspects of the major CEM techniques that a researcher may need to choose between to model a device, as well as provide insight into what steps they may take to alleviate some of their challenges. Our focus is on highlighting the main concepts without rigorously deriving all the details, which can be found in many textbooks and articles. After covering the fundamentals, we discuss more advanced topics related to the challenges of modeling multiscale devices with specific examples from superconducting circuit quantum devices. We conclude with a discussion on future research directions that will be valuable for improving the ability to successfully design increasingly more sophisticated superconducting circuit quantum devices. Although our focus and examples are taken from this area, researchers from other fields will still benefit from the details discussed here.

Elkin, Samuel T. [Virginia Tech., Blacksburg]↗

Device model for FETSIM circuit simulation program

A description of the MOS transistor used in the FETSIM analysis program is presented. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage.

Ramondetta, P.↗

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗