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FET comparator circuit detects discrete analog computer output levels without excessively loading the output amplifier of the computer. An FET common source amplifier is coupled by a differential amplifier to a bistable transistor flip-flop. This circuit provides a digital output for analog voltages above or below a predetermined level.
The development of power Field Effect Transistors (FET) operating in the 20 GHz frequency band is described. The major efforts include GaAs FET device development (both 1 W and 2 W devices), and the development of an amplifier module using these devices.
A cryogenic cooled, low-noise Field Effect Transistor (FET) amplifier assembly for use at 2.2 to 2.3 GHz was developed for the DSN to meet the requirements of a Very Long Baseline Interferometry (VLBI) upgrade. An amplifier assembly was developed at JPL that uses a commercial closed-cycle helium refrigerator (CCR) to cool a FET amplifier to an operating temperature of 15 K. A cooled probe waveguide-to-coaxial transition similar to that used in the research and development Ultra-Low-Noise S-band Traveling Wave Maser (TWM) is used to minimize input line losses. Typical performance includes an input flange equivalent noise contribution of 14.5 K, a gain slope of less than 0.05 dB/MHz across a bandwidth of 2.2 to 2.3 GHz, an input VSWR of 1.5:1 at 2.25 GHz, and an insertion gain of 45 + or - 1 dB across the bandwidth of 2.2 to 2.3 GHz. Three 2.3 GHz FET/CCR assemblies were delivered to the DSN in the spring of 1987.
Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.
Low-frequency, low-noise, low-power cryogenic electronics to read out photodetectors is being investigated for the star-tracking telescope of the Gravity Probe B spacecraft. We report our initial findings from evaluating more than 20 types of GaAs FETs, both commercial and non-commercial, for this application. Most exhibit useable dc characteristics at cryogenic temperatures, although gate leakage and hysteretic effects (presumably due to charge trapping) could be troublesome. Low-frequency noise (based primarily on grounded-gate measurements) at 4 K is '1/f-like' and for the quietest GaAs FETs appears to be at least as low as the lowest noise values reported for Si MOSFETs at 4 K. Further investigation is needed in several areas.
The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.
A statistical interpolation technique is presented for modeling GaAs FET S-parameter measurements for use in the statistical analysis and design of circuits. This is accomplished by interpolating among the measurements in a GaAs FET S-parameter data base in a statistically valid manner.
Most nonlinear circuit analysis programs that exist today were designed primarily for transient analysis. By incorporating more accurate models in simulation programs, accurate predictions of GaAs field effect transistors (FET) behavior can be accomplished. However, should the designer need to simulate GaAs FETs that operate at high DC-to-RF conversion efficiencies, a more sophisticated model is needed. A relevant and appropriate method is called harmonic-balance, as described by Quere et al.
A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.
A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.
The low noise and radiation-hard operation of the SOI Four-Gate transistor (G4-FET) is eperimentally demonstrated.
Field-effect transistors, with their high impedance and low noise, can effectively measure very low currents. To bring the FET up to electrometer standards (so that it can measure currents of, say, 10 (sup -13) amp) the designer must know where the noise is and what to do about it.
Metal oxide silicon field effect transistors /MOS FET/ as switching elements for low level commutator
Oxide isolated islands of N and P type silicon semiconductors by epitaxial deposition and etching for complimentary MOS-FET devices
Epitaxial deposition of P-type silicon into etche grooves in N-type silicon for P-N junction for complimentary MOS-FET devices
Properties of second-gate electrode of MOS-FET AND application as voltage-controlled integrator
Digital subsystem design and development employing n-channel and p-channel in MOS FET units in complimentary circuits in integrated circuit array