Low-frequency generation noise in junction field effect transistors.
LF noise generation in junction field effect transistors due to charge fluctuations
NOISE INTENSITY↗
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Microwave field effect transistor
Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.
Huang, Ho-Chung↗
Leakage and field emission in side-gate graphene field effect transistors
We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
High temperature operation to 500 °C of AlGaN graded polarization-doped field-effect transistors
AlGaN polarization-doped field-effect transistors were characterized by DC and pulsed measurements from room temperature to 500 °C in ambient. DC current-voltage characteristics demonstrated only a 70% reduction in on-state current from 25 to 500 °C and full gate modulation, regardless of the operating temperature. Near ideal gate lag measurement was realized across the temperature range that is indicative of a high-quality substrate and sufficient surface passivation. The ability for operation at high temperature is enabled by the high Schottky barrier height from the Ni/Au gate contact, with values of 2.05 and 2.76 eV at 25 and 500 °C, respectively. The high barrier height due to the insulatorlike aluminum nitride layer leads to an ION/IOFF ratio of 1.5 × 10 9 and 6 × 10 3 at room temperature and 500 °C, respectively. Transmission electron microscopy was used to confirm the stability of the heterostructure even after an extended high-temperature operation with only minor interdiffusion of the Ni/Au Schottky contact. The use of refractory metals in all contacts will be key to ensure a stable extended high-temperature operation.
36 MATERIALS SCIENCE↗
Logarithmic amplifier uses field effect transistors
Solid-state amplifier utilizes field effect transistors and planar junction diodes to provide a logarithmic response to a wide range of input signals.
Stewart, J. L.↗
High transconductance InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors
Pseudomorphic In0.15Ga0.85As/A10.15Ga0.85As modulation-doped field effect transistors (MODFET's) exhibiting extremely good dc characteristics have been successfully fabricated. dc transconductance in these strained-layer structures of 270 mS/mm was measured for 1-micron gate, normally-on devices at 300 K. Maximum drain current levels are 290 mA/mm, with excellent pinch-off and saturation characteristics. The transconductance increased to 360 mS/mm at 77 K while no persistent photoconductivity or drain collapse was observed. Preliminary microwave results indicate a 300-K current gain cutoff frequency of about 20 GHz. These results are equivalent to the best GaAs/AlGaAs MODFET results and are due in part to the improved transport properties and carrier confinement in the InGaAs quantum well.
Ketterson, A.↗
High-performance field effect transistors with self-assembled nanodielectrics
Field effect transistor devices comprising III-V semiconductors and organic gate dielectric materials, such dielectric materials as can afford flexibility in device design and fabrication.
Marks, Tobin J.↗
In-situ SiN{sub x}/InN structures for InN field-effect transistors
Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performance was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
A thick-film, insulated gate field effect transistor
Feasibility of fabricating thick film, insulated gate field effect transistor using integrated screened circuit technology
INTEGRATED CIRCUIT↗
Small Current Measurements with Insulated Gate Field Effect Transistor Electrometers
Small current measurements with insulated-gate field effect transistor electrometers
ELECTROMETER↗
Nano-textured high sensitivity ion sensitive field effect transistors
Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict the extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Internal additive noise effects in stochastic resonance using organic field effect transistor
Stochastic resonance phenomenon was observed in organic field effect transistor using poly(3-hexylthiophene), which enhances performance of signal transmission with application of noise. The enhancement of correlation coefficient between the input and output signals was low, and the variation of correlation coefficient was not remarkable with respect to the intensity of external noise, which was due to the existence of internal additive noise following the nonlinear threshold response. In other words, internal additive noise plays a positive role on the capability of approximately constant signal transmission regardless of noise intensity, which can be said “homeostatic” behavior or “noise robustness” against external noise. Furthermore, internal additive noise causes emergence of the stochastic resonance effect even on the threshold unit without internal additive noise on which the correlation coefficient usually decreases monotonically.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate
This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
TH-CD-201-12: Preliminary Evaluation of Organic Field Effect Transistors as Radiation Detectors
Purpose: To fabricate organic field effect transistors (OFETs) and evaluate their performance before and after exposure to ionizing radiation. To determine if OFETs have potential to function as radiation dosimeters. Methods: OFETs were fabricated on both Si/SiO{sub 2} wafers and flexible polymer substrates using standard processing techniques. Pentacene was used as the organic semiconductor material and the devices were fabricated in a bottom gate configuration. Devices were irradiated using an orthovoltage treatment unit (120 kVp x-rays). Threshold voltage values were measured with the devices in saturation mode and quantified as a function of cumulative dose. Current-voltage characteristics of the devices were measured using a Keithley 2614 SourceMeter SMU Instrument. The devices were connected to the reader but unpowered during irradiations. Results: Devices fabricated on Si/SiO2 wafers demonstrated excellent linearity (R{sup 2} > 0.997) with threshold voltages that ranged between 15 and 36 V. Devices fabricated on a flexible polymer substrate had substantially smaller threshold voltages (∼ 4 – 8 V) and slightly worse linearity (R{sup 2} > 0.98). The devices demonstrated excellent stability in I–V characteristics over a large number (>2000) cycles. Conclusion: OFETs have demonstrated excellent potential in radiation dosimetry applications. A key advantage of these devices is their composition, which can be substantially more tissue-equivalent at low photon energies relative to many other types of radiation detector. In addition, fabrication of organic electronics can employ techniques that are faster, simpler and cheaper than conventional silicon-based devices. These results support further development of organic electronic devices for radiation detection purposes. Funding Support, Disclosures, and Conflict of Interest: This work was funded by the Natural Sciences and Engineering Research Council of Canada.
60 APPLIED LIFE SCIENCES↗
Gate protective device for insulated gate field-effect transistors
Device, which protects insulated gate field-effect transistors, improves reliability through utilization of layers of conductive material on top of each alternating semiconductor material region. Separation of layers is necessary to prevent shorting out junctions between alternating regions.
Sunshine, R. A.↗
Field effect transistor and method of construction thereof
A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.
Fletner, W. R.↗
Porous-Floating-Gate Field-Effect Transistor
Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
Thakoor, Anilkumar P.↗
Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor
We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.
Pinto, N. J.↗