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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Dose measurement based on threshold shift in MOSFET arrays in commercial SRAMS

A new method using an array of MOS transistors isdescribed for measuring dose absorbed from ionizingradiation. Using the array of MOSFETs in a SRAM, a direct measurement of the number of MOS cells which change as a function of applied bias on the SRAM. Since the input and output of a SRAM used as a dosimeter is completely digital, the measurement of dose is easily accessible by a remote processing system.

SRAM dosimetry microdosimetry threshold shift↗
NASA NTRS1980

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.

Lieneweg, U.↗
NASA NTRS1977

The charge-flow transistor - A new MOS device

A new device, the charge-flow transistor (CFT), has been developed to achieve integrated MOS compatibility in sensor applications, such as gas, humidity, and fire detection, where one is interested in monitoring the transverse resistance of a thin film. The resistive material is incorporated into the gate structure of the CFT in such a way that there is a time delay between the application of the gate-to-source voltage and the appearance of a complete channel. This time delay depends on the resistivity of the thin film. A theory of device operation is presented, together with experimental results on the first CFT's. These results confirm the principles of operation, and demonstrate the utility of the CFT for making fully integrated sensing devices.

Senturia, S. D.↗
NASA NTRS1994

Nonvolatile programmable neural network synaptic array

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Tawel, Raoul↗
NASA NTRS1981

Method of making V-MOS field effect transistors utilizing a two-step anisotropic etching and ion implantation

A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.

Jhabvala, M. D.↗
NASA NTRS1970

Low-power integrated-circuit driver for ferrite-memory word lines

Composite circuit uses both n-p-n bipolar and p-channel MOS transistors /BIMOS/. The BIMOS driver provides 1/ ease of integrated circuit construction, 2/ low standby power consumption, 3/ bidirectional current pulses, and 4/ current-pulse amplitudes and rise times independent of active device parameters.

Katz, S.↗
NASA NTRS1974

Experimental investigation of a shielded complementary Metal-Oxide Semiconductor (MOS) structure

A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.

Lin, H. C.↗
NASA NTRS1975

Electrical and electronic devices and components: A compilation

Components and techniques which may be useful in the electronics industry are described. Topics discussed include transducer technology, printed-circuit technology, solid state devices, MOS transistors, Gunn device, microwave antennas, and position indicators.

Source record↗
NASA NTRS1975

Tunnel injection into gate oxide traps

An experimental method is described for measuring the density of oxide traps in the gate oxide of an MOS transistor as a function of energy and position near the silicon interface. Measurements are obtained from different oxide growth processes and after Co-60 irradiation. The results are related to long-term drift of threshold voltage.

Maserjian, J.↗
NASA NTRS1977

Device model for FETSIM circuit simulation program

A description of the MOS transistor used in the FETSIM analysis program is presented. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage.

Ramondetta, P.↗
NASA NTRS1980

Models of MOS and SOS devices

Quarterly report describes progress in three programs: dc sputtering machine for aluminum and aluminum alloys; two dimensional computer modeling of MOS transistors; and development of computer techniques for calculating redistribution diffusion of dopants in silicon on sapphire films.

Gassaway, J. D.↗
NASA NTRS1978

A study of trends and techniques for space base electronics

A sputtering system was developed to deposit aluminum and aluminum alloys by the dc sputtering technique. This system is designed for a high level of cleanliness and for monitoring the deposition parameters during film preparation. This system is now ready for studying the deposition and annealing parameters upon double-level metal preparation. A technique recently applied for semiconductor analysis, the finite element method, was studied for use in the computer modeling of two dimensional MOS transistor structures. It was concluded that the method has not been sufficiently well developed for confident use at this time. An algorithm was developed for confident use at this time. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program which was developed was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients.

Trotter, J. D.↗
NASA NTRS1978

Trends and techniques for space base electronics

A system was developed for depositing aluminum and aluminum alloys by the D.C. sputtering technique. This system which was designed for a high level of cleanliness and ion monitoring the deposition parameters during film preparation is ready for studying the deposition and annealing parameters upon double level metal preparation. The finite element method was studied for use in the computer modeling of two dimensional MOS transistor structures. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions typical of those used at MSFC. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients. Data are given showing both two dimensional effects and the evolution of the junction depth, sheet resistance and integrated dose with redistribution time.

Gassaway, J. D.↗
NASA NTRS1982

A monolithic lead sulfide-silicon MOS integrated-circuit structure

A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

Jhabvala, M. D.↗
NASA NTRS1983

Annual Conference on Nuclear and Space Radiation Effects, Gatlinburg, TN, July 18-21, 1983, Proceedings

Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.

Source record↗
NASA NTRS1983

Pinhole array capacitor for oxide integrity analysis

The integrity of the metal-poly oxide and the gate oxide was evaluated for several 5-micron CMOS-bulk processes. The pinhole array capacitor consists of diffused and poly fingers that form a network of MOS transistors (elements), which are capped by a deposited oxide and metal layer. The smallest structure used in this study contained about 15,000 elements and the largest structure contained about 68,000 elements. Each structure was divided into several subarrays. The structures are placed a number of times on each wafer. From a yield analysis of the subarrays, the elements per defect were found to be typically in excess of 50,000 elements/defect for the metal-poly oxide and 100,000 elements/defect for the gate oxide. From the switching behavior of the transistors, the gate oxide defects were tentatively identified as gate-to-body shorts rather than gate-to-diffusion shorts.

Buehler, M. G.↗
NASA NTRS1986

Reducing Sodium Contamination in MOS Devices

Method of removing positive ions from oxides in metal-oxide-semiconductor (MOS) transistors and intergrated circuits ensure freedom from contamination by sodium and other mobile positive ions. Electric field applied during oxide growth to push mobile Na + ions to surface. After cooling from growth temperature, field turned off and Na + contaminated surface layer etched away. New method intended to suplement established methods of minimizing ion contamination, such as scrupulous cleanliness in processing, purging with hydrogen chloride to react with and remove contaminants, and growing extra-thick gate oxide, then etching it to remove large portion of contaminants concentrated near surface.

Dehaye, R. F.↗