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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Determination Of LETs Of SRAMs By Use Of A Laser

Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.

Kim, Quiesup↗
NASA NTRS1983

Single event upset (SEU) of semiconductor devices - A summary of JPL test data

The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).

Nichols, D. K.↗
NASA NTRS1985

Trends in parts susceptibility to single event upset from heavy ions

New test data have been combined with published data to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. These data have been arranged to exibit the SEU susceptibility of devices by function, technology, and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1998

RH1020 Single Event Clock Upset Summary Report

This report summarizes the testing and analysis of "single event clock upset' in the RH1020. Also included are SEU-rate predictions and design recommendations for risk analysis and reduction. The subject of "upsets" in the RH1020 is best understood by using a model consisting of a global clock buffer and a D-type flip-flop as the basic memory unit. The RH1020 is built on the ACT 1 family architecture. As such, it has one low-skew global clock buffer with a TTL-level input threshold that is accessed via a single dedicated pin. The clock signal is driven to full CMOS levels, buffered, and sent to individual row buffers with one buffer per channel. For low-skew performance, the outputs of all of the RH1020 row buffers are shorted together via metal lines, as is done in the A1020B. All storage in the RH1020 consists of routed flip-flops, constructed with multiplexors and feedback through the routing segments. A simple latch can be constructed from a single (combinatorial or C) module; an edge-triggered flip-flop is constructed using two concatenated latches. There is no storage in the I/O modules. The front end of the clock buffering circuitry, at a common point relative to the row buffer, is a sub-circuit that was determined to be the most susceptible to heavy ions. This is due, in part, to its smaller transistors compared to the rest of the circuitry. This conclusion is also supported by SPICE simulations and an analysis of the heavy ion data, described in this report. The edge triggered D flip-flop has two single-event-upset modes. Mode one, called C-module upset, is caused by a heavy ion striking the C-module's sensitive area on the silicon and produces a soft single bit error at the output of the flip-flop. Mode two, called clock upset, is caused by a heavy ion strike on the clock buffer, generating a runt pulse interpreted as a false clock signal and consequently producing errors at the flip-flop outputs. C-module upset sensitivity in the RH1020 is essentially the same as that of its ACT 1 siblings (A1020, A1020A and A1020B), which were well tested, analyzed, and documented in the literature.

Katz, Richard B.↗
NASA NTRS1986

Trends in parts susceptibility to single event upset from heavy ions

New test data from the Jet Propulsion Laboratory (JPL), The Aerospace Corporation, Rockwell International (ANAHEIM) and IRT have been combined with published data of JPL and Aerospace to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. This data has been arranged to exhibit the SEU susceptibility of devices by function, technology and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1985

Cosmic ray simulation and testing program

Single event upset (SEU) and latchup vulnerabilities were determined for a number of parts of interest to NASA space programs. In cases where a threshold linear energy transfer (LET) for SEU could be measured, an upset rate in a low inclination Space Shuttle orbit was computed. The predicted upset rates are extremely low, except for the devices with LET thresholds below the geomagnetic cutoff for altitude and inclination of the Space Shuttle orbit. While some of the devices do exhibit latchup, the cross sections and threshold LETs are such that the risk associated with flying these devices in low, near equatorial orbits is small if not negligible.

Kolasinski, W. A.↗
NASA NTRS1997

Antifuse FPGA for Space Applications

This paper presents viewgraphs of Antifuse FPGA (Field Programmable Gate Array) for Space Applications. The topics include: 1) A32140DX TID Test; 2) A1280XL Proton Test; 3) SEU (Single Event Upsets) Rate Calculation; 4) Recent Products Test; 5) A1460A TID (Traveling Ionospheric Disturbances) Test; 6) I100 Proton Test; 7) 100/RHI100 SEU Test; 8) I100/RH100 TID Test; 9) A1020S TID Test; 10) TID Charge Pump Failure; 11) Radiation Testing; and SEE (Single Event Effects) Test Setup.

Wang, Jih-Jong↗
NASA NTRS2024

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗
NASA NTRS1989

Effects of cosmic rays on single event upsets

Assistance was provided to the Brookhaven Single Event Upset (SEU) Test Facility. Computer codes were developed for fragmentation and secondary radiation affecting Very Large Scale Integration (VLSI) in space. A computer controlled CV (HP4192) test was developed for Terman analysis. Also developed were high speed parametric tests which are independent of operator judgment and a charge pumping technique for measurement of D(sub it) (E). The X-ray secondary effects, and parametric degradation as a function of dose rate were simulated. The SPICE simulation of static RAMs with various resistor filters was tested.

Venable, D. D.↗
NASA NTRS1990

Single event induced transients in I/O devices - A characterization

The results of single-event upset (SEU) testing performed to evaluate the parametric transients, i.e., amplitude and duration, in several I/O devices, and the impact of these transients are discussed. The failure rate of these devices is dependent on the susceptibility of interconnected devices to the resulting transient change in the output of the I/O device. This failure rate, which is a function of the susceptibility of the interconnected device as well as the SEU response of the I/O device itself, may be significantly different from an upset rate calculated without taking these factors into account. The impact at the system level is discussed by way of an example.

Newberry, D. M.↗
NASA NTRS2014

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Single Event Upset Testing↗
NASA NTRS2015

Single Event Effects in FPGA Devices 2014-2015

This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single event upset (SEU)↗
NASA NTRS2016

Single Event Effects in FPGA Devices 2015-2016

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single Event Upset (SEU) Testing↗