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Document summarizes 15 studies of single-event upsets covering 60 different types of semiconductor devices. Studies discussed in document include verification of basic reactions induced by heavy ions and protons and surveys of latchup and bit-flip susceptibility of several types of devices and device-fabrication technologies.
Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.
Experimental study presents examples of empirical modeling of single-event upset in negatively-doped-source/drain metal-oxide-semiconductor static random-access memory cells. Data supports adoption of simplified worst-case model in which cross sectionof SEU by ion above threshold energy equals area of memory cell.
Report provides nearly comprehensive body of data on single-event upsets due to irradiation by heavy ions. Combines new test data and previously published data from governmental and industrial laboratories. Clear trends emerge from data useful in predicting future performances of devices.
Two reports describe preliminary theoretical and experimental studies based on method described in "Laser Scanner Tests For Single-Event Upsets" (NPO-18216). Laser-scan and heavy-ion data found correlated within factor of two. Method of testing for single-event upsets intended to overcome disadvantages of, complement, and/or substitute for more-expensive cyclotron-testing method, which does not provide spatial resolution.
This viewgraph presentation gives an overview of Field Programmable Gate Arrays (FPGA) in the space environment and design techniques. Details are given on the effects of the space radiation environment, total radiation dose, single event upset, single event latchup, single event transient, antifuse technology and gate rupture, proton upsets and sensitivity, and loss of functionality.
Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.
This paper presents an analysis of the sensitivity of single event upset (SEU) rate predictions to changes in the direct ionization-inducing environment. An examination based on the nature of the SEU rate equation is presented for the case in which the perturbation is constant across varying particle linear energy transfer (LET). It is shown that the relative variation in SEU rate is equal to the relative perturbation in flux. Results are also presented for the case in which the environment perturbations exist in small LET bins. Through this analysis it is shown that the relative variation in expected SEU rate is equal to that in flux only for the LET regime in which the product of the cross section and differential flux is maximum.
An apparatus for and method of eliminating single event upsets (or SEU) in combinational logic are used to prevent error propagation as a result of cosmic particle strikes to the combinational logic. The apparatus preferably includes a combinational logic block electrically coupled to a delay element, a latch and an output buffer. In operation, a signal from the combinational logic is electrically coupled to a first input of the latch. In addition, the signal is routed through the delay element to produce a delayed signal. The delayed signal is routed to a second input of the latch. The latch used in the apparatus for preventing SEU preferably includes latch outputs and a feature that the latch outputs will not change state unless both latch inputs are correct. For example, the latch outputs may not change state unless both latch inputs have the same logical state. When a cosmic particle strikes the combinational logic, a transient disturbance with a predetermined length may appear in the signal. However, a function of the delay element is to preferably provide a time delay greater than the length of the transient disturbance. Therefore, the transient disturbance will not reach both latch inputs simultaneously. As a result, the latch outputs will not permanently change state in error due to the transient disturbance. In addition, the output buffer preferably combines the latch outputs in such a way that the correct state is preserved at all times. Thus, combinational logic with protection from SEU is provided.
A summary of single event upset data for 42 device types (including RAMs, 4-bit slices, microprocessors, 4-bit counters, and flip-flops) studied at 11 different accelerator tests (performed chiefly with the Berkeley 88-inch cyclotron and the Cal Tech Van de Graaff) is presented. All bipolar and NMOS RAMs were found to be SEU sensitive, some with very low LET thresholds. Some CMOS or CMOS/SOS RAMs were hard; and the CMOS microprocessors were hard, but the bipolar and NMOS microprocessors were soft. Several devices were found to exhibit a cross section that depends strongly on LET, even when the LET is well above the LET threshold. A ranking of hardness is presented for the logic devices tested.
Heavy secondary ions do not significantly alter device responses. Conclusion that external reaction products cause no significant alteration of single-event-upset response based on comparison of data obtained from both lidded and unlidded devices and for proton beams impinging at angles ranging from 0 degrees to 180 degrees with respect to chip face. Study also found single-event-upset cross section increases only modestly as proton energy increased to 590 MeV, characteristic of maximum energies expected in belts of trapped protons surrounding Earth and Jupiter.
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.
Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.
This paper analyzes data from a single-event upset experiment conducted at the Los Alamos National Laboratory. Statistical tools, based on well-known x(sup 2) hypothesis testing theory, are used to determine if sequences of upsets can be modeled as a homogeneous Markov chain of a specific order. The experiment consisted of radiating a new experimental flight control computer (FCC) with a high intensity neutron beam while the FCC controlled a simulation of a Boeing 737. The analyzed data is a sequence of states that indicates when the FCC is under an upset condition.
Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.
We propose a method for the application of single event upset (SEU) data towards the analysis of complex systems using transformed reliability models (from the time domain to the particle fluence domain) and space environment data.
We propose a method for the application of single event upset (SEU) data towards the analysis of complex systems using transformed reliability models (from the time domain to the particle fluence domain) and space environment data.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.