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At least 37 records · Page 2

Comparison of TID Response and SEE Characterization of Single and Multi Level High Density NAND Flash Memories

Heavy ion single-event measurements and TID response for 8Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. In general, these commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The charge pump survived up to 600 krads.

nonvolatile memory

FPGA Flash Memory High Speed Data Acquisition

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Gonzalez, April

Single-Event Upset in Flash Memories

This paper discusses single-event upset effets in flash memories, using heavy ions at the Texas A&M cyclotron. Initial results are presented for one manufacturer that compare uspet in the individual memory elemts with the more complex funtion failure modes that occur in the internal state machine and its control registers. This device is designed to function with either 5-V or 3.3-V power supply levels for read operations, but requires an additional 5 or 12-V power supply for write and erase operations.

Flash

Disturb testing in flash memories

Non-volatile memory technology as defined by NAND architecture flash memory continues to lead the process scaling and device shrinking efforts of the entire integrated circuit industry. 45- nm technology nodes are now producing commercial 32Gb devices. These latest 32Gb devices are pioneering new charge trapping memory cell technologies using metal gates and high-k dielectric materials. These cells are called TANOS and consist of tantalum-nitride, aluminum oxide (high k material), nitride, oxide, and silicon. Such high-density memories continue to revolutionize commercial electronics in terms of new high-speed data architectures and significant reductions in overall power and weight consumption. In stark contrast, nearly all science-based interplanetary and earth-orbiting NASA spacecraft are still designing in and around mid-1980s-level non-volatile technology with 1Mb Electrically Erasable Read-Only Memory (EEPROM) devices. NASA has typically shunned the use of modern flash devices because of radiation and reliability concerns due to the commercial-offthe– shelf (COTS) nature of the NAND flash technology. Given the significant potential increases in overall system capability these modern flash devices could bring to NASA missions, it is important to continue to investigate these devices. This report will investigate certain portions of the reliability performance of NAND flash devices, specifically the disturb properties. Understanding the possible limitations such new non-volatile memory technology presents to NASA is the goal of this report.

Freie, Michael

Radiation Tests on 2Gb NAND Flash Memories

We report on SEE and TID tests of highly scaled Samsung 2Gbits flash memories. Both in-situ and biased interval irradiations were used to characterize the response of the total accumulated dose failures. The radiation-induced failures can be categorized as followings: single event upset (SEU) read errors in biased and unbiased modes, write errors, and single-event-functional-interrupt (SEFI) failures.

NAND circuits

Observation of Low-Energy Proton Direct Ionization in a 72-Layer 3D NAND Flash Memory

Single-event upsets are observed in a 72-layer 3D NAND flash memory operated in single-level cell mode after low-energy proton (500 keV-1.2 MeV) and heavy ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of low energy protons within the memory stack, and Monte Carlo simulations are correlated with the experimental data. Direct ionization by low-energy protons is identified by three-dimensional data analysis and the energy dependence of device sensitive cross-section. Heavy ion data is also presented for comparison.

Direct ionization

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

latency

MT29F512G08AUCBBH8-6IT:B NAND Flash Memory Total Ionizing Dose Test Report

The purpose of this test was to characterize the Micron 512 GB NAND (MT29F512G08AUCBBH8-6IT:B) flash memory parameter degradation for total dose response. In the test, the device was exposed to high dose rate (HDR) irradiations using gamma radiation. Device parameters such as leakage currents, quantity of upset bits and overall chip and die health were investigated.

TID

Effect of Radiation and Endurance on Pulsed Programming of Commercial NAND Flash Memory

Independent and coupled effects of radiation and endurance on commercial NAND Flash memory is studied using pulsed programming enabled by interrupting the programming command at the chip-level. The effects of total ionization dose (TID) and endurance stress increase and decrease, respectively, the number of pulses needed to program an entire page. The coupled effect of endurance stress and TID appear to exhibit linear correlation. A neutral electron/ hole trap model is evaluated and correlates well with our results.

Narasimham, Avyaya Jayanthi

TID, SEE and radiation induced failures in advanced flash memories

We report on TID and SEE tests of multi-level and higher density flash memories. Stand-by currents and functionality tests were used to characterize the response of radiation-induced failures. The radiation-induced failures can be categorized as followings: SEU read errors during irradiation, stuck-bit read errors verified post-irradiation, write errors, erase failures, multiple upsets, and single-event latch up.

Scheick, Leif Z.

TID and SEE Response of an Advanced Samsung 4G NAND Flash Memory

Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment.

Oldham, Timothy R.