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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Wide Bandgap Semiconductors for Extreme Temperature and Radiation Environments

With their greater voltage breakdowns, higher current limitations, and faster switching speeds, wide bandgap semiconductors are increasing in market application over the traditionally dominant silicon devices. Silicon carbide semiconductors have been increasing the efficiency and reducing the footprint of modern power electronics, and the increased electron mobility of gallium nitride semiconductors have been increasing the switching frequencies of radio frequency circuits. In extreme temperature (>225°C) applications and high radiation environments such as low earth orbit, deep space, and terrestrial nuclear reactors, silicon-based semiconductors degrade rapidly. Wide bandgap semiconductors are poised to disrupt the market for sensing, instrumentation, and communication circuitry in these hazardous environments by increasing the lifetime, safety, and reliability. This report outlines the advantages of using wide bandgap semiconductor materials in extreme temperature and radiation environments.

36 MATERIALS SCIENCE↗
NASA NTRS1981

Silicon superlattices: Theory and application to semiconductor devices

Silicon superlattices and their applicability to improved semiconductor devices were studied. The device application potential of the atomic like dimension of III-V semiconductor superlattices fabricated in the form of ultrathin periodically layered heterostructures was examined. Whether this leads to quantum size effects and creates the possibility to alter familiar transport and optical properties over broad physical ranges was studied. Applications to improved semiconductor lasers and electrondevices were achieved. Possible application of silicon sperlattices to faster high speed computing devices was examined. It was found that the silicon lattices show features of smaller fundamental energyband gaps and reduced effective masses. The effects correlate strongly with both the chemical and geometrical nature of the superlattice.

Moriarty, J. A.↗
DOE OSTI2023

Fabrication-robust silicon photonic devices in standard sub-micron silicon-on-insulator processes

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach–Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.

Rizzo, Anthony (ORCID:000000034752797X)↗
DOE OSTI2023

Investigation of the silicon coated film characteristics on tungsten surface in EAST fusion device

Siliconization using 10 % SiD 4 + 90 % He assisted by ion cyclotron range of frequency discharge (ICRF) or glow discharge (GD) was performed in EAST with full tungsten (W) diverters. It was found that the coated Si film on W sample at a higher baking temperature (160 °C) was smoother than that at a lower baking temperature (60 °C). This was mainly because physically adsorbed gaseous impurities were released at a higher baker temperature. This process improved the adhesion between the film and the surface of W. An increase in the ICRF working power from 20 kW to 40 kW further increased the Si content and the film thickness by 1.5 times. The cleaning efficiency of ICRF on the surface of the W sample before siliconization was higher at 40 kW than that at 20 kW, which facilitated the removal of oxides and other compounds from the surface of W. The ratio of silicon/oxygen (Si/O) and the thickness improved considerably due to greater ionization and deposition of SiD 4 . Additionally, siliconization via GD was more uniform and 1.5 nm thicker than that via ICRF, which was because of the greater working gas pressure, coating duration, and homogeneity in GD. These results might be used as a reference for evaluating the effect of siliconization on plasma performance and its application in fusion devices.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2025

Laser-Induced Spectral Diffusion of T Centers in Silicon Nanophotonic Devices

Color centers in silicon are emerging as spin-photon interfaces operating at telecommunication wavelengths. The nanophotonic device integration of silicon color centers via ion implantation leads to significant optical-linewidth broadening, which makes indistinguishable photon generation challenging. Here, we study the optical spectral diffusion of T centers in a silicon photonic crystal cavity. We investigate the linewidth-broadening timescales and origins by measuring the temporal correlations of the resonance frequency under different conditions. Spectral hole-burning measurements reveal no spectral broadening at short timescales from 102 ns to 725 ns. We probe broadening at longer timescales using a check pulse to herald the T-center frequency and a probe pulse to measure the frequency after a wait time. The optical resonance frequency is stable up to 3 ms in the dark. Laser pulses below the silicon band gap applied during the wait time lead to linewidth broadening. Our observations establish laser-induced processes as the dominant spectral-diffusion mechanism for T centers in devices and inform materials and feedback strategies for indistinguishable photon generation.

Zhang, Xueyue↗
NASA NTRS2012

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Akturk, Akin↗
DOE OSTI2022

Efficient black silicon photovoltaic devices with enhanced blue response

A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low opant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nano-structured or black silicon surface on the light-receiving surface, through which the emitter is formed by diffusion. The nano structures of the black silicon are formed in a manner that does not result in gold or another high-recombination metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostructures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.

Oh, Jihun↗
NASA NTRS1987

High-temperature electronics

In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

Seng, Gary T.↗
NASA NTRS2014

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Hoenk, Michael E.↗
NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗
NASA NTRS1992

An overview of silicon carbide device technology

Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.

Neudeck, Philip G.↗
NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗
NASA NTRS2008

Method for implementation of back-illuminated CMOS or CCD imagers

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Pain, Bedabrata↗