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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

High-temperature electronics

In recent years, there was a growing need for electronics capable of sustained high-temperature operation for aerospace propulsion system instrumentation, control and condition monitoring, and integrated sensors. The desired operating temperature in some applications exceeds 600 C, which is well beyond the capability of currently available semiconductor devices. Silicon carbide displays a number of properties which make it very attractive as a semiconductor material, one of which is the ability to retain its electronic integrity at temperatures well above 600 C. An IR-100 award was presented to NASA Lewis in 1983 for developing a chemical vapor deposition process to grow single crystals of this material on standard silicon wafers. Silicon carbide devices were demonstrated above 400 C, but much work remains in the areas of crystal growth, characterization, and device fabrication before the full potential of silicon carbide can be realized. The presentation will conclude with current and future high-temperature electronics program plans. Although the development of silicon carbide falls into the category of high-risk research, the future looks promising, and the potential payoffs are tremendous.

Seng, Gary T.↗
NASA NTRS2014

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Hoenk, Michael E.↗
NASA NTRS1999

Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1-(micron)meter MOSFET's with Epitaxial and (delta)-Doped Channels

A detailed three-dimensional (3-D) statistical 'atomistic' simulation study of fluctuation-resistant sub-0.1-(micron)meter MOSFET architectures with epitaxial channels and delta doping is presented. The need for enhancing the fluctuation resistance of the sub-0.1-(micron)meter generation transistors is highlighted by presenting summarized results from atomistic simulations of a wide range of conventional devices with uniformly doped channel. According to our atomistic results, the doping concentration dependence of the random dopant-induced threshold voltage fluctuations in conventional devices is stronger than the analytically predicted fourth-root dependence. As a result of this, the scaling of such devices will be restricted by the "intrinsic" random dopant-induced fluctuations earlier than anticipated. Our atomistic simulations confirm that the introduction of a thin epitaxial layer in the MOSFET's channel can efficiently suppress the random dopant-induced threshold voltage fluctuations in sub-0.1-(micron)meter devices. For the first time, we observe an "anomalous" reduction in the threshold voltage fluctuations with an increase in the doping concentration behind the epitaxial channel, which we attribute to screening effects. Also, for the first time we study the effect of a delta-doping, positioned behind the epitaxial layer, on the intrinsic threshold voltage fluctuations. Above a certain thickness of epitaxial layer, we observe a pronounced anomalous decrease in the threshold voltage fluctuation with the increase of the delta doping. This phenomenon, which is also associated with screening, enhances the importance of the delta doping in the design of properly scaled fluctuation-resistant sub-0.1-(micron)meter MOSFET's. Index Terms-Doping, fluctuations, MOSFET, semiconductor device simulation, silicon devices, threshold.

Asenov, Asen↗
NASA NTRS1992

An overview of silicon carbide device technology

Recent progress in the development of silicon carbide (SiC) as a semiconductor is briefly reviewed. This material shows great promise towards providing electronic devices that can operate under the high-temperature, high-radiation, and/or high-power conditions where current semiconductor technologies fail. High quality single crystal wafers have become available, and techniques for growing high quality epilayers have been refined to the point where experimental SiC devices and circuits can be developed. The prototype diodes and transistors that have been produced to date show encouraging characteristics, but by the same token they also exhibit some device-related problems that are not unlike those faced in the early days of silicon technology development. Although these problems will not prevent the implementation of some useful circuits, the performance and operating regime of SiC electronics will be limited until these device-related issues are solved.

Neudeck, Philip G.↗
NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗
NASA NTRS2008

Method for implementation of back-illuminated CMOS or CCD imagers

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Pain, Bedabrata↗
NASA NTRS1974

Study of the use of Metal-Oxide-Silicon (MOS) devices for particulate detection and monitoring in the earth's atmosphere

A metal-oxide-silicon (MOS) capacitor-type particulate sensor was evaluated for use in atmospheric measurements. An accelerator system was designed and tested for the purpose of providing the necessary energy to trigger the MOS-type sensor. The accelerator system and the MOS sensor were characterized as a function of particle size and velocity. Diamond particles were used as particulate sources in laboratory tests. Preliminary tests were performed in which the detector was mounted on an aircraft and flown in the vicinity of coal-fired electric generating plants.

Brooks, A. D.↗
NASA NTRS2018

SiAl Alloy Feedhorn Arrays: Material Properties, Feedhorn Design, and Astrophysical Applications

We present here a study of the use of the SiAl alloy CE7 for the packaging of silicon devices at cryogenic temperatures. We report on the development of baseplates and feedhorn arrays for millimeter wave bolometric detectors for astrophysics. Existing interfaces to such detectors are typically made either of metals, which are easy to machine but mismatched to the thermal contraction profile of Si devices, or of silicon, which avoids the mismatch but is difficult to directly machine. CE7 exhibits properties of both Si and Al, which makes it uniquely well suited for this application. We measure CE7 to a) superconduct below a critical transition temperature, T (sub c), 1.2 K, b) have a thermal contraction profile much closer to Si than metals, which enables simple mating, and c) have a low thermal conductivity which can be improved by Au-plating. Our investigations also demonstrate that CE7 can be machined well enough to fabricate small structures, such as #0-80 threaded holes, to tight tolerances (approximately 25 microns) in contrast with pure silicon and similar substrates. We have fabricated CE7 baseplates being deployed in the 93 gigahertz polarimetric focal planes used in the Cosmology Large Angular Scale Surveyor (CLASS). We also report on the development of smooth-walled feedhorn arrays made of CE7 that will be used in a focal plane of dichroic 150/220 gigahertz detectors for the CLASS High-Frequency camera.

Ali, Aamir M.↗
NASA NTRS2012

Fabrication of a Cryogenic Terahertz Emitter for Bolometer Focal Plane Calibrations

A fabrication process is reported for prototype emitters of THz radiation, which operate cryogenically, and should provide a fast, stable blackbody source suitable for characterization of THz devices. The fabrication has been demonstrated and, at the time of this reporting, testing was underway. The emitter is similar to a monolithic silicon bolometer in design, using both a low-noise thermometer and a heater element on a thermally isolated stage. An impedance-matched, high-emissivity coat ing is also integrated to tune the blackbody properties. This emitter is designed to emit a precise amount of power as a blackbody spectrum centered on terahertz frequencies. The emission is a function of the blackbody temperature. An integrated resistive heater and thermometer system can control the temperature of the blackbody with greater precision than previous incarnations of calibration sources that relied on blackbody emission. The emitter is fabricated using a silicon- on-insulator substrate wafer. The buried oxide is chosen to be less than 1 micron thick, and the silicon device thickness is 1-2 microns. Layers of phosphorus compensated with boron are implanted into and diffused throughout the full thickness of the silicon device layer to create the thermometer and heater components. Degenerately doped wiring is implanted to connect the devices to wire-bondable contact pads at the edge of the emitter chip. Then the device is micromachined to remove the thick-handle silicon behind the thermometer and heater components, and to thermally isolate it on a silicon membrane. An impedance- matched emissive coating (ion assisted evaporated Bi) is applied to the back of the membrane to enable high-efficiency emission of the blackbody spectrum.

Chervenak, James↗
NASA NTRS2014

High Input Voltage Discharge Supply for High Power Hall Thrusters Using Silicon Carbide Devices

A power processing unit for a 15 kW Hall thruster is under development at NASA Glenn Research Center. The unit produces up to 400 VDC with two parallel 7.5 kW discharge modules that operate from a 300 VDC nominal input voltage. Silicon carbide MOSFETs and diodes were used in this design because they were the best choice to handle the high voltage stress while delivering high efficiency and low specific mass. Efficiencies in excess of 97 percent were demonstrated during integration testing with the NASA-300M 20 kW Hall thruster. Electromagnet, cathode keeper, and heater supplies were also developed and will be integrated with the discharge supply into a vacuum-rated brassboard power processing unit with full flight functionality. This design could be evolved into a flight unit for future missions that requires high power electric propulsion.

Electric Propulsion↗
NASA NTRS1982

Deep impurity trapping concepts for power semiconductor devices

High voltage semiconductor switches using deep impurity doped silicon now appear feasible for high voltage (1-100 kV), high power (10 Kw) switching and protection functions for future space power applications. Recent discoveries have demonstrated several practical ways of gating deep impurity doped silicon devices in planar configurations and of electrically controlling their characteristics, leading to a vast array of possible circuit applications. A new family of semiconductor switching devices and transducers are possible based on this technology. New deep impurity devices could be simpler than conventional p-n junction devices and yet use the same basic materials and processing techniques. In addition, multiple functions may be possible on a single device as well as increased ratings.

Sundberg, G. R.↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗