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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

High temperature↗
NASA NTRS2006

A Novel, Free-Space Optical Interconnect Employing Vertical-Cavity Surface Emitting Laser Diodes and InGaAs Metal-Semiconductor-Metal Photodetectors for Gbit/s RF/Microwave Systems

Emerging technologies and continuing progress in vertical-cavity surface emitting laser (VCSEL) diode and metal-semiconductor-metal (MSM) photodetector research are making way for novel, high-speed forms of optical data transfer in communication systems. VCSEL diodes operating at 1550 nm have only recently become commercially available, while MSM photodetectors are pushing the limits of contact lithography with interdigitated electrode widths reaching sub micron levels. We propose a novel, free-space optical interconnect operating at about 1Gbit/s utilizing VCSEL diodes and MSM photodetectors. We report on development, progress, and current work, which are as follows: first, analysis of the divergent behavior of VCSEL diodes for coupling to MSM photodetectors with a 50 by 50 m active area and second, the normalized frequency response of the VCSEL diode as a function of the modulating frequency. Third, the calculated response of MSM photodetectors with varying electrode width and spacing on the order of 1 to 3 m as well as the fabrication and characterization of these devices. The work presented here will lead to the formation and characterization of a fully integrated 1Gbit/s free-space optical interconnect at 1550 nm and demonstrates both chip level and board level functionality for RF/microwave digital systems.

Savich, Gregory R.↗
NASA NTRS1985

Test chip assembler and test program generator

One of the major problems in working at the geometry level for the generation of either test structure or functional circuit designs is the amount of labor involved in the design phase. To reduce the amount of labor involved in both the design and test of the structures used, JPL has developed a design and test program consisting of a Test Chip Assembler (TCA) and a Test Program Generator (TPG), which creates the geometrical description of the structures and generates the necessary test information using a high-level language. This system reduces the design time for a test chip by a factor of 30. To analyze the data obtained from wafer probing, a statistical package called STMJPL was developed. Some of the capabilities of the JPL software (STMJPL) are described.

Pina, C. A.↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRS2004

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

power switch slice (PSS)↗
DOE OSTI2025

A compact low-level RF control system for advanced concept compact electron linear accelerator

A compact low-level RF (LLRF) control system based on RF system-on-chip (RFSoC) technology has been designed for the Advanced Concept Compact Electron Linear-accelerator (ACCEL) program, which has challenging requirements in both RF performance and size, weight, and power consumption (SWaP). The compact LLRF solution employs the direct RF sampling technique of RFSoC, which samples the RF signals directly without any analog upconversion and downconversion. Compared with the conventional heterodyne based architecture used for the LLRF system of a linear accelerator (LINAC), the elimination of analog mixers can significantly reduce the size and weight of the system, especially with LINAC requiring a larger number of RF channels. Based on the requirements of ACCEL, a prototype LLRF platform has been developed, and the control schemes have been proposed. The prototype LLRF system demonstrated magnitude and phase fluctuation levels below 1% and 1° on the flattop of a 2 μs RF pulse. The LLRF control schemes proposed for ACCEL are implemented with a prototype hardware platform. In conclusion, this paper will introduce the new compact LLRF solution and summarize a selection of experimental test results of the prototype itself and with the accelerating structure cavities designed for ACCEL.

Liu, C. [SLAC National Accelerator Laboratory (SLA↗
NASA NTRS1982

Chip level simulation of fault tolerant computers

Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault tolerant computer was modeled. An efficient approach to functional fault simulation was developed. Simulation software was also developed.

Armstrong, J. R.↗
DOE OSTI2025

RFSoC based digital low level RF control firmware and software suite (mimo_llrf) v1.0

It features a framework of a firmware and software architecture in support of building a digital low-level RF control system for accelerators, where precised digital RF generation and measurement are needed across many RF channels. It primarily supports the Xilinx RFSoC chips (xczu48dr, xczu47dr, xczu29dr) and their evaluation boards (zcu208, zcu216), for a highly integrated solution enabling the need for synchronous low-level RF systems, including: multi-tile synchronization, external reference for sampling clocks, deterministic delay, aligned NCO phase for digital mixers, and built-in EPICS IOC.

Du, Qiang [Lawrence Berkeley National Laboratory (↗
NASA NTRS2017

Distributed Timing and Localization (DiGiTaL)

The Distributed Timing and Localization (DiGiTaL) system provides nano satellite formations with unprecedented,centimeter-level navigation accuracy in real time and nanosecond-level time synchronization. This is achieved through the integration of a multi-constellation Global Navigation Satellite System (GNSS) receiver, a Chip-Scale Atomic Clock (CSAC), and a dedicated Inter-Satellite Link (ISL). In comparison, traditional single spacecraft GNSS navigation solutions are accurate only to the meter-level due to the sole usage of coarse pseudo-range measurements. To meet the strict requirements of future miniaturized distributed space systems, DiGiTaL uses powerful error-cancelling combinations of raw carrier-phase measurements which are exchanged between the swarming nano satellites through a decentralized network. A reduced-dynamics estimation architecture on board each individual nano satellite processes the resulting millimeter-level noise measurements to reconstruct the fullformation state with high accuracy.

Small Spacecraft↗
DOE OSTI2024

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole↗
DOE OSTI2024

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade

The ETROC2 prototype for CMS MTD Endcap Timing Layer (ETL) upgrade 520__ $$aThe Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit. The ETROC2 is the first full size (16x16) prototype design with the front-end based on and scaled up from the ETROC1 (4x4). The readout designs at pixel and global level and the system interfaces are all new and are compatible with the final chip specifications in terms of functionality. The ETROC2 is intended as a learning chip, as a stepstone to the ETROC3 which is intended as the pre-production design. The ETROC2 design and test results will be presented.

Gong, Datao↗
NASA NTRS2004

Modular, Adaptive, Reconfigurable Systems: Technology for Sustainable, Reliable, Effective, and Affordable Space Exploration

In order to execute the Vision for Space Exploration, we must find ways to reduce cost, system complexity, design, build, and test times, and at the same time increase flexibility to satisfy multiple functions. Modular, Adaptive, Reconfigurable System (MARS) technologies promise to set the stage for the delivery of system elements that form the building blocks of increasingly ambitious missions involving humans and robots. Today, space systems are largely specialized and built on a case-by-case basis. The notion of modularity however, is nothing new to NASA. The 1970's saw the development of the Multi-Mission Modular spacecraft (MMS). From 1980 to 1992 at least six satellites were built under this paradigm, and included such Goddard Space Flight Center missions as SSM, EUVE, UARS, and Landsat 4 and 5. Earlier versions consisted of standard subsystem "module" or "box" components that could be replaced within a structure based on predefined form factors. Although the primary motivation for MMS was faster/cheaper integration and test, standardization of interfaces, and ease of incorporating new subsystem technology, it lacked the technology maturity and programmatic "upgrade infrastructure" needed to satisfy varied mission requirements, and ultimately it lacked user buy-in. Consequently, it never evolved and was phased out. Such concepts as the Rapid Spacecraft Development Office (RSDO) with its regularly updated catalogue of prequalified busses became the preferred method for acquiring satellites. Notwithstanding, over the past 30 years since MMS inception, technology has advanced considerably and now modularity can be extended beyond the traditional MMS module or box to cover levels of integration, from the chip, card, box, subsystem, to the space system and to the system-of-systems. This paper will present the MARS architecture, cast within the historical context of MMS. Its application will be highlighted by comparing a state-of-the-art point design vs. a MARS-enabled lunar mission, as a representative robotic case design.

Esper, Jaime↗
NASA NTRS1975

Open coil structure for bubble-memory-device packaging

Concept has several important advantages over close-wound system: memory and coil chips are separate and interchangeable; interconnections in coil level are eliminated by packing memory chip and electronics in single structure; and coil size can be adjusted to optimum value in terms of power dissipation and field uniformity.

Chen, T. T.↗
NASA NTRS1989

Chip Advancer For GPS Receiver

Instrument errors made negligible. For each integration interval, both delay and rate of change of delay initialized to small fraction of chip - for example, to order of 10 to the negative 7th power - thereby making feedback control and extraction of delay highly accurate and flexible. With appropriate selection of sampling rate relative to chip rate, commensurability errors reduced to extremely small levels. In Global Positioning System (GPS) receiver, pseudorandom code sequence generated by simple digital logic incorporating effects of time, delay, and rate of change of delay. Flexibility in starting time and sum interval very useful in aligning correlation interval with beginnings and endings of data bits.

Meehan, Thomas K.↗
NASA NTRS2004

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗
NASA NTRS1997

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Fang, Wai-Chi↗