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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS1976

On the applicability of integrated circuit technology to general aviation orientation estimation

The criteria of the significant value of the panel instruments used in general aviation were examined and kinematic equations were added for comparison. An instrument survey was performed to establish the present state of the art in linear and angular accelerometers, pressure transducers, and magnetometers. A very preliminary evaluation was done of the computers available for data evaluation and estimator mechanization. The mathematical model of a light twin aircraft employed in the evaluation was documented, the results of the sensor survey and the results of the design studies were presented.

Debra, D. B.↗
NASA NTRS1978

Reclaiming hybrid integrated circuits

Reclamation method consists of opening very small hole in package and shaking out trapped particles. Procedure is performed in dry box through which an inert gas is flowing to insure no room air enters package. Acoustic transducer monitors sound of vibrating particles. Amplifier produces audio and oscilloscope output. Hole is sealed with heated solder form.

Ebel, G.↗
NASA NTRS1978

Custom large scale integrated circuits for spaceborne SAR processors

The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for missions such as SEASAT-A, Venus orbital imaging radar (VOIR), and shuttle imaging radar (SIR) are summarized. Several azimuth correlator architectures that are suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft applications are reported in the context of expected space mission launch dates. The preliminary design of a custom LSI time-domain azimuth correlator device (ACD) being developed for use in future SAR processors is detailed.

Tyree, V. C.↗
NASA NTRS1978

Complementary DMOS-VMOS integrated circuit structure

A high speed CMOS formed on a single semiconductor substrate includes a DMOS having an asymmetric channel and a VMOS with a relatively short channel length. The short channel length of the VMOS is achieved by forming a double diffusion along one edge of a V groove, or ion implanting boron into the apex of the V groove and diffusing a single layer to a relatively deep depth along both edges of the groove.

Jhabvala, M. O.↗
NASA NTRS1978

Custom large scale integrated circuits for spaceborne SAR processors

The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for such missions as Seasat-A, Venus Orbital Imaging Radar, and Shuttle Imaging Radar are summarized. Several azimuth correlator architectures suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft application is examined in the context of the expected launch dates. In particular, it is demonstrated that a custom LSI device is practical for a system as complex as the DMSP.

Tyree, V. C.↗
NASA NTRS1981

CADAT integrated circuit artwork program

Versatile, ready-to-use program (ARTWORK) converts artwork data into mask patterns. ARTWORK generates signals for controlling mask-fabricating equipment. Extensive utility package enables user to create new pattern libraries, develop and incorporate new cells, and perform systems orientation functions. Program is written in FORTRAN IV.

Kvelthau, R. L.↗
NASA NTRS1977

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Woo, D. S.↗
NASA NTRS1979

Simulation of cosmic-ray induced soft errors and latchup in integrated-circuit computer memories

Soft errors have been induced in solid-state static RAM's by iron nuclei from the Lawrence Berkeley Laboratory (LBL) Bevalac, in experiments designed to prove the ability of iron-group cosmic rays to generate such errors. Subsequently, various delidded device types were tested in beams of argon and krypton ions from the LBL 88-inch Cyclotron, at energies near 2 MeV/nucleon. The latter tests showed that some devices are essentially immune to bit error while others are quite susceptible. Good agreement was obtained with model predictions in cases where the latter exist. Latchup, whose cause is attributed to individual heavy ions, was also observed in some device types.

Kolasinski, W. A.↗
NASA NTRS1978

User's manual for large-scale integrated circuit layout check program

A computer program is described that checks for the correctness of chip design layout generated by the Banning Placement Routing Folding program (PRF) by verifying agreement between a specified circuit design and a corresponding computer generated circuit layout as stored on the Artwork (PRF output) tape. An example computer run is included.

Source record↗
NASA NTRS1981

An evaluation of the Intel 2920 digital signal processing integrated circuit

The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

Heller, J.↗
NASA NTRS1979

Thermally grown oxide and diffusions for automatic processing of integrated circuits

A totally automated facility for semiconductor oxidation and diffusion was developed using a state-of-the-art diffusion furnace and high temperature grown oxides. Major innovations include: (1) a process controller specifically for semiconductor processing; (2) an automatic loading system to accept wafers from an air track, insert them into a quartz carrier and then place the carrier on a paddle for insertion into the furnace; (3) automatic unloading of the wafers back onto the air track, and (4) boron diffusion using diborane with plus or minus 5 percent uniformity. Processes demonstrated include Wet and dry oxidation for general use and for gate oxide, boron diffusion, phosphorous diffusion, and sintering.

Kennedy, B. W.↗
NASA NTRS1983

Etching Integrated Circuits

20-page report reviews methods available for etching specific layers on wafers and discusses automation techniques and features on one particular automated system. Compares two major etching methods, chemical (wet) and plasma (dry), and discusses areas in need of development. Methods covered include "dip-and-dunk" manual method of chemical etching, automated chemical etching, and plasma etching.

Kennedy, B. W.↗
NASA NTRS1981

Activation energies of thermal annealing of radiation-induced damage in n- and p-channels of CMOS integrated circuits. II

The procedures described by Danchenko et al. (1980) are applied to devices of RCA's Z-process (100,000 rad-hard). A thermal annealing investigation of the Z-process reveals an annealing behavior of the p-channels that is anomalous when compared with the p-channels of the commercial and J-processes. It is noted that the thermal annealing-induced shift of the threshold potential extends far below the original value; this necessitated the development of a new mathematical treatment, the treatment presented in the paper.

Danchenko, V.↗
NASA NTRS1984

Optical Testing of Integrated Circuits

Optical spot-raster scanner produces weighted photoresponse image (PI) of operating CMOS IC. Digital analysis of PI's, which correlates differences in PI's with electrical behavior of IC, shows promise both as 100-percent screening method for use in IC manufacture and as diagnostic tool in IC development.

Erickson, J.↗
NASA NTRS1983

Microwave monolithic integrated circuit development for future spaceborne phased array antennas

The development of fully monolithic gallium arsenide (GaAs) receive and transmit modules suitable for phased array antenna applications in the 30/20 gigahertz bands is presented. Specifications and various design approaches to achieve the design goals are described. Initial design and performance of submodules and associated active and passive components are presented. A tradeoff study summary is presented highlighting the advantages of distributed amplifier approach compared to the conventional single power source designs.

Anzic, G.↗
NASA NTRS1982

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

Woo, D. S.↗
NASA NTRS1984

Development of standardized specifications for screening space level integrated circuits and semiconductors

Standardized methods are established for screening of JAN B microcircuits and JANTXV semiconductor components for space mission or other critical applications when JAN S devices are not available. General specifications are provided which outline the DPA (destructive physical analysis), environmental, electrical, and data requirements for screening of various component technologies. This standard was developed for Air Force Space Division, and is available for use by other DOD agencies, NASA, and space systems contractors for establishing common screening methods for electronic components.

Source record↗