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At least 55 records · Page 3

Test Structures For Bumpy Integrated Circuits

Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

Buehler, Martin G.↗

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗

Pilot-Scale Testing of an Integrated Circuit for the Extraction of Rare Earth Minerals and Elements from Coal and Coal Byproducts Using Advanced Separation Technologies

The primary objective of this project was to develop and demonstrate an integrated pilot-scale circuitry for recovering high-value rare earth elements (REEs) from coal and coal byproducts. The target performance was to produce a mixed REE product with content of at least two percent by weight on a dry mass basis in a cost-effective and environmentally benign manner. During the first nine months of the project period (Phase 2 Budget Period 2), pilot plant construction was completed including all field site startup activities such as permitting, engineering design, procurement/bidding, unit fabrication, site construction, equipment installation, module assembly, safety training, and circuit shakedown. During the remaining 21 months of project period (Phase 2 Budget Period 3), detailed field-testing activities were performed including feedstock sample collection and preparation, exploratory testing, circuit modification, detailed parametric study, and performance optimization. A detailed techno-economic analysis was performed based on the pilot plant testing findings which provided various scenarios for REE production. The project successfully accomplished the proposed target performance by producing mixed rare earth oxide (REO) with greater than 90% purity by weight in a continuous pilot scale operation from two distinctly different coarse refuse materials (i.e., West Kentucky No. 13 and Fire Clay coal seams), and at least three secondary sources (i.e., heap leach process and naturally formed acid mine drainage system). Project partners included the University of Kentucky, Virginia Tech, West Virginia University, Alliance Coal, Blackhawk Mining, Mineral Refining Company, and Mineral Separation Technologies. The pilot scale test facility was constructed at a former mining complex owned by Alliance Natural Resource Partners (Alliance Coal). The site was rehabilitated to accommodate the equipment installation, construction and fabrication, electrical power requirement, water line management and containment. The process units constructed and installed included X-ray sorting unit, crushing and grinding unit, physical separation unit, acid leaching unit, solvent extraction unit, and wastewater management unit. A rare earth mineral concentration unit was constructed as a standalone unit for flexible operation. A detailed environmental assessment and control plan was carried out to identify and quantify any potential impacts of the pilot-scale processing circuitry on the human and eco-system health and well-being. Corresponding mitigation strategies and control measures were provided. A conceptual flowsheet was developed to effectively remove thorium and uranium from high purity rare earth oxide mix or any potential radionuclide enriched stream. The two distinct feedstock materials were secured from the Blackhawk Mining Complex in eastern Kentucky where the Fire Clay (Hazard No. 4) seam is processed. The West Kentucky No. 13 (Baker) coarse refuse material was collected from an active process stream at an Alliance coal preparation plant located in western Kentucky. Characterization analysis indicated that both of feed materials generated from the two sources contained >300 ppm of TREEs on a dry whole mass basis which met the requirements for a qualified feed stock. The two feedstocks were further upgraded using a dual x-ray sorter to prepare the feed material for hydrometallurgical circuit. Thermal treatment on feed material prior to leaching was found to: 1) improve the leaching recovery of REEs, 2) increase the leaching kinetics, and 3) allow the leaching reaction to occur at lower acidity. Roasting at 600°C was selected as the pre-treatment condition for both West Kentucky No. 13 and Fire Clay coarse refuse material. Over 40% of leaching recovery was achieved by roasting West Kentucky No. 13 material having a top particle size of 3 mm in the pilot scale operation using 1.2M sulfuric acid leaching at 75OC. Initial pilot scale testing involved continuous operation of the pilot plant for 94 hours. The leaching unit was operated at solid-to-liquid ratio of 1 to 10 (w/v) using 0.5M sulfuric acid solution at a temperature of 75°C. The continuous solvent extraction circuit utilized rougher and cleaner units with DEHPA and TBP as the extractants. An innovative stripping circuit was developed to accumulate the REE concentration in the stripping solution to a level above 600 ppm. A bleed stream from the recycled strip solution was treated using oxalic acid precipitation which produced a high grade rare earth oxalate. The oxalate product was roasted to remove the oxalate which produced a rare earth oxide product having a purity greater 90%. Due to high concentrations of contaminant ions in the pregnant leach solution (PLS), a modified flowsheet was developed that involved pre-concentration of the REEs using multiple stages of precipitation and redissolution. The advantage of this process was improved removal of contamination before the downstream purification process and a significant cost reduction relative to the circuit that utilized the solvent extraction process. The modified circuitry included processes involving leaching, multistage precipitation, redissolution, and oxalate precipitation followed by roasting of the oxalate product. The circuit produced a mixed REO that was 92.96% pure from the initial test. A detailed parametric test plan was carried out which involved varying key parameters including solids feed rate, acid flowrate, acid concentration, multistage precipitation pH, redissolution pH, oxalate precipitation dosage and pH. The response variables included REE recovery, contaminant recovery, REO product grade and overall chemical consumption. Test results indicated that the acid-to-solid ratio is the key parameter to leaching efficiency as performance deteriorated with an increase in solids concentration. The optimal pH determined for REE precipitation and redissolution was 6.5 and 2.5, respectively. Additional tests were conducted to further improve the flowsheet. Recirculating a portion of the PLS to the feed of the leach tanks improved the leaching performance by lowering the pH of the leaching system and reducing the contamination recovery by shortening the residence time. Moreover, the removal of Al prior to REE precipitation significantly reduced the oxalic acid consumption in the oxalate precipitation circuit. The modified circuit produced over 90% grade REO by weight from both West Kentucky No. 13 and Fire Clay coarse refuse material in pilot scale continuous test programs. A case analysis model was developed to project the REE and major contaminants concentration in each PLS stream based on the leaching condition, pH cut point, and oxalic acid dosage. A correlation was established using empirical and semi-empirical models. Using the models, chemical consumption required for each stage was predicted based on the projected performance of the hydrometallurgy circuit. After identifying the optimum conditions, validation tests were carried out for the treatment of both West Kentucky No. 13 and Fire Clay coarse refuse materials in the pilot plant. The actual circuit performance and chemical consumptions were very close to the model predictions. Other than the two coarse refuse sources, several secondary feedstocks were also tested in the pilot plant facility. A “heap leach” system was constructed using the coarse refuse material generated from cleaning the West Kentucky No. 13 seam coal. Using the two stage SX rougher and cleaner circuit, a concentrate with a grade >90% REO was produced while recovering >97% of the REEs from the heap leach PLS. Naturally generated acid mine drainage (AMD) from West Kentucky No.13 mine was processed using the multistage precipitation circuit in the pilot plant in a test conducted for a period of 32 hours. The final grade of the mix RE oxide produced from the AMD was 90.84% with an overall circuit recovery of 64%. The primary source of REE was the selective precipitation steps involving iron and aluminum rejection. The hydrophobic-hydrophilic separation (HHS) process was proven to effectively recover coal from fine waste materials. For REM recovery, the HHS process was able to produce concentrates at grades of approximately 1.8% REE on an ash basis; however, recovery values were typically low, <10%, under the optimal conditions determined in the laboratory-scale testing. Staged testing of the pilot-scale HHS process for coal recovery and semi-continuous laboratory testing for REM testing showed that a total concentration ratio of more than 15x was observed for the REM recovery process. A circuit simulation package was developed for REE extraction and purification using a spreadsheet-based platform (Microsoft Excel). The REESim circuit simulation package is configured to track the mass and volume flows of components passing through a series of unit operations specified and configured by the user. The mass rates can then be utilized by the user to determine important performance indicators such as product mass yields, concentrate purity levels, element-by-element recoveries, and so forth. The techno-economic analysis showed that the roasting and leaching operations were the most expensive capital items, each contributing approximately 30% to the total capital cost. One notable contributor to the high production costs was the low REE recovery observed in the pilot scale trials. The product basket price was shown to have a strong influence on the economic viability of the scenarios, with the scandium price being the most significant influencer. Operating cost was shown to be extremely sensitive to REE recovery, REE feed grade, and leaching acid consumption. An analysis of ten different scenarios for a 500 t/h commercial operation revealed that three were economically favorable, producing internal rates of return varying from 27.7% to 33.1% and payback periods of 4 to 5 years. The project successfully developed and demonstrated a process to recover REEs from coal and coal byproducts in a pilot-plant operation which consistently produced over 90% grade REO mix from varies types of feedstocks. Commercialization analysis showed that the technology readiness level successfully achieved TRL 6 at the end of the project and demonstrated the need and the potential for scaling the process to further advance the technologies toward the goal of providing a domestic supply of REEs at a commercial scale.

01 COAL, LIGNITE, AND PEAT↗

Total Ionizing Dose Effects in Bipolar and BiCMOS Devices

This paper describes total ionizing dose (TID) test results performed at JPL. Bipolar and BiCMOS device samples were tested exhibiting significant degradation and failures at different irradiation levels. Linear technology which is susceptible to low-dose dependency (ELDRS) exhibited greater damage for devices tested under zero bias condition.

radiation effects↗

Total-dose radiation effects data for semiconductor devices, volume 2

Total ionizing dose radiation test data on integrated circuits are analyzed. Tests were performed with the electron accelerator (Dynamitron) that provides a steady state 2.5 MeV electron beam. Some radiation exposures were made with a Cobalt-60 gamma ray source. The results obtained with the Cobalt-60 source are considered an approximate measure of the radiation damage that would be incurred by an equivalent dose of electrons.

Price, W. E.↗

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

High temperature↗

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

electronic packaging↗

Five-Segment Interconnection For Electromigration Tests

Proposed integrated-circuit conductive pattern intended for use in electromigration lifetime testing of interconnection lines of integrated circuits. Designed for collection of statistics on electromigration from smallest possible area. Includes 5 interconnection segments with Kelvin voltage taps, with total of 12 contact pads, and provides for simultaneous measurements on all of segments. Attempts to minimize thermal gradients within each segment and conforms to guidelines on electromigration test structures promulgated by National Institute of Standards and Technology (NIST).

Hannaman, David J.↗

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Van Vonno, N. W.↗

Development of automated test procedures and techniques for LSI circuits

Testing of large scale integrated (LSI) logic circuits was considered from the point of view of automatic test pattern generation. A system for automatic test pattern generation is described. A test generation algorithm is presented that can be applied to both combinational and sequential logic circuits. Also included is a programmed implementation of the algorithm and sample results from the program.

Carroll, B. D.↗

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

LaBel, Kenneth A.↗

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗