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Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.
The object of this program is to improve the detectivity of the pyroelectric detector with the ultimate goal of operation at or near the temperature noise limit. Two general areas of investigation are undertaken. The first is to improve responsivity through the use of new materials. The second is directed toward reduction of noise and will be effected with improved field effect transistor characteristics, and improved electroding of the pyroelectric material. The review of the literature on pyroelectric materials continues. From this, several materials have already been selected for investigation, and several were tested.
Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.
Method is applied in middle of fabrication process: (a) after mask region is formed, diffused-boron region is etched; (b) etching is left incomplete for ion implantation; (c) boron ions are implanted into region to define accurately crucial geometry of V-groove; (d) groove is etched to completion, forming two well-defined diffusion regions that serve as source and drain of transistor. Remaining process is conventional.
A research program for the development of a 10.6 micron HgCdTe photodiode/GaAs field effect transistor amplifier package for use at cryogenic temperatures (77k). The photodiode/amplifier module achieved a noise equivalent power per unit bandwidth of 5.7 times 10 to the 20th power W/Hz at 2.0 GHz. The heterodyne sensitivity of the HgCdTe photodiode was improved by designing and building a low noise GaAs field effect transistor amplifier operating at 77K. The Johnson noise of the amplifier was reduced at 77K, and thus resulted in an increased photodiode heterodyne sensitivity.
In the case of modern infrared focal planes, one of the major problems is related to the noise contribution of the cooled, impedance-matching device used as the preamplifier stage in the detector electronics system. An ideal preamp device should have the low-noise advantages of a buried-channel device and operate isothermally with the low-temperature detector array. The Ge JFET might provide this ideal device. A testing program with Ge JFETs is discussed. It is concluded that germanium JFETs offer an attractive alternative for cryogenic preamplifier designs. They operate well with high transconductance and low noise at LHe temperatures. It is believed that these devices point the way for the development of large, integrated-array, long wavelength, infrared focal planes which incorporate germanium detectors, germanium load resistors, and germanium preamplifiers within the same monolithic structure.
Test were conducted to measure the performance of the 20-GHz solid state, proof-of-concept amplifier. The amplifier operates over the 17.7 to 20.2-GHz frequency range and uses high power gallium arsenide field effect transistors. The amplifier design and test methods are briefly described. NASA and contractor performance data are compared.
A MOSFET structure having a biased gate covered with an insulator is described. The insulator is of such a thickness as to render the structure capable of giving a measure of accumulated charge. The structure is also capable of being used in a stacked structure as a particle spectrometer.
New metal-oxide-semiconductor field-effect transistors designed for source-follower preamplifiers operating at liquid-helium temperatures in conjunction with infrared detectors. Lower thresholds and offset give CryoFET's greater dynamic range and linearity than conventional MOSFET's at low temperatures and facilitates pair balancing to reduce offsets in output. Reduces heat loading of cryogenic system, extending life, reliability, and performance of cryogenic infrared instruments.
A temperature independent device is presented which uses a quantum well structure and delta doping within the channel. The device requires a high delta doping concentration within the channel to achieve a constant Hall mobility and carrier concentration across the temperature range 300-1.4 K. Transistors were RF tested using on-wafer probing and a constant G sub max and F sub max were measured over the temperature range 300-70 K.
A novel cryogenic design of a source follower per detector (SFD) direct readout multiplexer is demonstrated. This design has proven to be a good prototype for the development of new low-noise large-area cryogenic multiplexers. In the absence of clocking noise, the readout demonstrates as low as about 30 electrons of rms read noise. There is still an excess noise component feeding through when the array is clocked, which manifests itself only at the lower temperatures. The shape of this component is dependent on a number of the bias voltages, and especially on the temperature of the chip. Analysis of the noise spectral density of the unit cell under various bias conditions shows that there is an excess spectral noise component at the lower temperatures.
Over the course of this program, very extensive progress was made in Ka-band GaAs technology. At the beginning of the program, odd-shaped VPE MESFET wafers were used. A breakthrough in power and efficiency was achieved with highly doped (8 x 10(exp 17) cm(exp -3) MBE grown MESFET material. We obtained power of 112 mW with 16 dB gain and 21.6% efficiency at 34 GHz with a monolithic 50-100-250 micron amplifier. The next breakthrough came with the use of heterostructures grown by MBE (AlGaAs/InGaAs where the InGaAs is highly doped). This allowed us to achieve high power density with high efficiency. A benchmark 40% efficiency was achieved with a single-stage 100 micron MMIC at 32.5 GHz. The corresponding three-stage 50-100-250 micron amplifier achieved 180 mW with 23 dB gain and 30.3% efficiency. The next breakthrough came with 3-inch MBE grown PHEMT wafers incorporating an etch-stop layer for the gate recess (using RIE). Again, state-of-the-art performances were achieved: 40% efficiency with 235 mW output power and 20.7 dB gain. The single-stage 2 x 600 micron chip demonstrated 794 mW output power with 5 dB gain and 38.2% power-added efficiency (PAE). The Ka-band technology developed under this program has promise for extensive use: JPL demonstrated 32 GHz phased arrays with a three-stage amplifier developed under this contract. A variation of the three-stage amplifier was used successfully in a 4 x 4 phased array transmitter developed under another NASA contract.
A shunt switch comprised of a field-effect transistor (Q.sub.1) is employed to commutate a current-fed inverter (10) using thyristors (SCR1, SCR2) or bijunction transistors (Q.sub.2, Q.sub.3) in a full bridge (1, 2, 3, 4) or half bridge (5, 6) and transformer (T.sub.1) configuration. In the case of thyristors, a tapped inverter (12) is employed to couple the inverter to a dc source to back bias the thyristors during commutation. Alternatively, a commutation power supply (20) may be employed for that purpse. Diodes (D.sub.1, D.sub.2) in series with some voltage dropping element (resistor R.sub.12 or resistors R.sub.1, R.sub.2 or Zener diodes D.sub.4, D.sub.5) are connected in parallel with the thyristors in the half bridge and transformer configuration to assure sharing the back bias voltage. A clamp circuit comprised of a winding (18) negatively coupled to the inductor and a diode (D.sub.3) return stored energy from the inductor to the power supply for efficient operation with buck or boost mode.
The power systems for use in NASA space missions must work reliably under harsh conditions including radiation, thermal cycling, and exposure to extreme temperatures. Gallium nitride semiconductors show great promise, but information pertaining to their performance is scarce. Gallium nitride N-channel enhancement-mode field effect transistors made by EPC Corporation in a 2nd generation of manufacturing were exposed to radiation followed by long-term thermal cycling in order to address their reliability for use in space missions. Results of the experimental work are presented and discussed.
This study was undertaken to determine the single event effect (SEE) susceptibility of two different MOSFET components. Heavy-ion testing was conducted at the Lawrence Berkeley National Laboratory (LBNL) Berkeley Accelerator Space Effects (BASE) Facility 88” Cyclotron. Its purpose was to evaluate these devices as candidates for use on Goddard Modular SmallSat Architecture (GMSA) adapter board for the GTOSat project.
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To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.
A process and product providing a High Efficiency Microwave Power Amplifier (HEMPA) which propagates S-Band microwave frequency square waves; utilizing a program simulating FETs at high DC-to-RF efficiencies, which analyses linear elements of selected FETs in a frequency domain, and non-linear elements of the FETs in a time domain, and converts the time domain values into the frequency domain, and performs DC and S-parameter simulated measurements based on predefined data for each FET. Individual FET parameters are extracted and isolated by converting the S-parameters to admittance or impedance parameters to derive FET models for each FET, which the program uses to provide a final output of a HEMPA circuit based on iterative simulations of an amplification circuit utilizing microwave topology and frequencies. Iterative simulations of the amplification circuit analyze output values of a plurality of cascaded stages of the FETs, which are arranged in a push-pull configuration.