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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

Characteristics of Single-Event Upsets in a Fabric Switch (ADS151)

Abstract-Two types of single event effects - bit errors and single event functional interrupts - were observed during heavy-ion testing of the AD8151 crosspoint switch. Bit errors occurred in bursts with the average number of bits in a burst being dependent on both the ion LET and on the data rate. A pulsed laser was used to identify the locations on the chip where the bit errors and single event functional interrupts occurred. Bit errors originated in the switches, drivers, and output buffers. Single event functional interrupts occurred when the laser was focused on the second rank latch containing the data specifying the state of each switch in the 33x17 matrix.

Buchner, Stephen↗
NASA NTRS2009

Virtex-4VQ dynamic and mitigated single event upset characterization summary

This report is the result of funding by the NASA Electronic Parts and Packaging Program (NEPP) and the combined efforts of members within the Xilinx Radiation Test Consortium (XRTC), sometimes known as the Xilinx Single Event Effects (SEE) Test Consortium. The XRTC is a voluntary association of aerospace entities, including leading aerospace companies, universitie and national laboratories, combining resources to characterize reconfigurable, field programmable gate arrays (FPGAs) for aerospace applications. Previous publications of Virtex-4 radiation results are for commercial (non-epitaxial) devices; see, for example, Refs. 1–5. A notable exception is Ref. 6, which presents XRTC upset measurements of storage elements in the PowerPC405s in the XQR4VFX60. This work represents a continuation of the efforts reported in the “Virtex-4QV Static SEU Characterization Summary” [7]. The contents of this report describe various Single Event Functional Interrupt (SEFI) and Single Event Upset (SEU) modes seen while dynamically exercising the clocked resources within Virtex-4 devices and the corresponding mitigation techniques related to the aforementioned observed SEFI modes.

Allen, Gregory↗
NASA NTRS2015

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Field Programmable Gate Array (FPGA)↗
NASA NTRS1988

Full temperature single event upset characterization of two microprocessor technologies

Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.

Nichols, Donald K.↗
NASA NTRS1988

Effects of cosmic rays on single event upsets

The efforts at establishing a research program in space radiation effects are discussed. The research program has served as the basis for training several graduate students in an area of research that is of importance to NASA. In addition, technical support was provided for the Single Event Facility Group at Brookhaven National Laboratory.

Lowe, Calvin W.↗
NASA NTRS1985

Single event upset immune integrated circuits for Project Galileo

Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.

Giddings, A. E.↗
NASA NTRS1991

Multiple single event upsets in CMOS static rams

The occurrence of multiple upset errors during ground tests can contaminate the data and lead to error cross sections which are too high. In space, multiple errors may produce higher upsets than predicted and if they occur in single words they can defeat error detection and correction hardware. This investigation involves data which were taken during an experimental study of dose imprint effects in static memories. The results show that multiple errors occurred mainly for heavy ions with high linear energy transfers and with the majority of these in the soft upset sections of the dose-imprinted memory samples. The percentages of the total number of errors which were singles, doubles, and triplets, were determined as a function of LET, dose, and soft or hard section of the devices. The experimental observations are compared to the predictions of simple binomial statistics.

Stassinopoulos, E. G.↗
NASA NTRS1981

Investigation for single-event upset in MSI devices

The reported investigation shows that low-power TTL, standard TTL, low-power Schottky, and Schottky devices are all subject to upset by heavy ions. Low-power Schottky was the most sensitive of the device technologies tested. No evidence was found to correlate sensitivity to cosmic rays with any particular device manufacturer. The probability of upset of the logic devices is comparable to that of RAM's on a per-flip-flop basis, based on RAM data obtained by Kolasinski et al. (1979). The testing was performed by subjecting the devices to 120 MeV krypton ions from a cyclotron.

Woods, J. P.↗
NASA NTRS1982

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Kolasinski, W. A.↗