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Different aspects of advanced surface mount package technology have been investigated. Three key areas included the assembly reliability of conventional Surface Mount (SM), Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs).
Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.
Re-Active Passive (RAP) devices have been developed to control low frequency (<1000 Hz) noise transmission through a panel. These devices use a combination of active, re-active, and passive technologies packaged into a single unit to control a broad frequency range utilizing the strength of each technology over its best suited frequency range. The RAP device uses passive constrained layer damping to cover the relatively high frequency range (>200 Hz), reactive distributed vibration absorber) to cover the medium frequency range (75 to 250 Hz), and active control for controlling low frequencies (<200 Hz). The device was applied to control noise transmission through a panel mounted in a transmission loss test facility. Experimental results are presented for the bare panel, and combinations of passive treatment, reactive treatment, and active control. Results indicate that three RAP devices were able to increase the overall broadband (15-1000 Hz) transmission loss by 9.4 dB. These three devices added a total of 285 grams to the panel mass of 6.0 kg, or approximately 5%, not including control electronics.
Different aspects of advanced surface mount package technology have been investigated for aerospace applications.
This paper summarizes and reports a radiation hardened spacecraft high temperature, high reliability Sensor/Circut Integrated Packaging Technology.
The results of a study carried out in order to manufacture and verify the quality of chip-on-board (COB) packaging technology are presented. The COB, designed for space applications, was tested under environmental stresses, temperature cycling, and temperature-humidity-bias. Both robustness in space applications and in environmental protection on the ground-complete reliability without hermeticity were searched for. The epoxy-parylene combinations proved to be superior to other materials tested.
In relation to the Rosetta surface science package, the benefits of the application of advanced microelectronics packaging technologies and other output from the Mars environmental survey (MESUR) integrated microelectronics study are reported on. The surface science package will be designed to operate for tens of hours. Its limited mass and power consumption make necessary a highly integrated design with all the instruments and subunits operated from a centralized control and information management subsystem.
The intent of this presentation is to give a brief look into the future of electronic packaging for microspacecraft applications. Advancements in electronic packaging technology areas have developed to the point where a system engineer's visions, concepts, and requirements for a microspacecraft can now be a reality. These new developments are ideal candidates for microspacecraft applications. These technologies are capable of bringing about major changes in how we design future spacecraft while taking advantage of the benefits due to size, weight, power, performance, reliability , and cost. This presentation will also cover some advantages and limitations of surface mount technology (SMT), multichip modules (MCM), and wafer scale integration (WSI), and what is needed to implement these technologies into microspacecraft.
The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.
This paper presents the results of NASA’s COLDTECH development entitled “Cold Survivable Distributed Motor Controller (CSDMC)”. This work addresses the need to lower the mass, power and volume of the motor control electronics and its associated cabling. Landed payload mass of ocean world missions typically requires a spacecraft launch mass of 7-10x the landed mass due to the required propellant to get the payload to the surface. Reduction of landed mass leads to cheaper, more frequent missions and/or increased science return. This work addresses this need by developing a distributed electronics architecture, which places control and power electronics near or at actuators and instruments. The outcome of this effort will result in a 10X reduction in harness mass, enabling a significant increase in science payload which then enables more capable sample acquisition, delivery and analysis systems on these missions. Placing the control and power conversion electronics at or near the actuators or instruments is the cornerstone of our distributed architecture. To do this, we developed the technology necessary to distribute the electronics and place them on a shared interface and power bus. This enables a significant reduction in cable mass along with its associated complexity. This allows spacecraft designers to take advantage of volume at the extremities that would normally not be utilized. In this paper we discuss the technologies and system design to achieve these goals in support of ocean world missions. These technologies include the development of our motor control modules, a point of load regulator and isolated converter modules along with the packaging technology necessary to allow our electronics to survive the extreme temperatures.
A review of low cost large solid rocket motors developed at the Lewis Research Center is given. An estimate is made of the total cost reduction obtainable by incorporating this new technology package into the rocket motor design. The propellant, case material, insulation, nozzle ablatives, and thrust vector control are discussed. The effect of the new technology on motor cost is calculated for a typical expandable 260-in. booster application. Included in the cost analysis is the influence of motor performance variations due to specific impulse and weight changes. It is found for this application that motor costs may be reduced by up to 30% and that the economic attractiveness of future large solid rocket motors will be improved when the new technology is implemented.
Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.
Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Different aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included the assembly reliability of conventional Surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Diffenent aspects of advanced surface mount package technology have been investigated for aerospace applications. Three key areas included understanding assembly reliability behavior of conventional surface Mount, Ball Grid Arrays (BGAs), and Chip Scale Packages.
Current inverter technologies used in electric vehicles (EVs) are bulky, heavy, and expensive. The performance of the inverter is also limited by the traditional Si-based semiconductor and packaging technology. These constraints are responsible for extra weight and volume in the vehicle that reduces the driving range along with usable space within the vehicle. Moreover, operating temperature restrictions, and boundaries on the inverter location within the vehicle drastically reduces the inverter performance. Thus an improved inverter design is required for next generation electric vehicles. The objective of this project was to research, develop and demonstrate a highly integrated WBG power module targeting the next generation of plugin hybrid electric vehicles (PHEVs). This power module needed to be functionally and mechanically optimized for General Motors (GM) traction inverter architecture. General Motors was the prime contractor, led the project, and oversaw the design, build, and test of the integrated power module. Virginia Polytechnic Institute and State University (VT) performed modeling and simulation tasks as well as power module design support. Monolith Semiconductor, Inc provided SiC dies and consulted on devices for the inverter. Oak Ridge National Laboratory (ORNL) performed power module technology evaluations, design evaluations of interconnect options, and performed material analysis and cross-sectioning of die activities.
Package manufacturers are now offering commercial-off-the-shelf column grid array (COTS CGA) packaging technologies in high-reliability versions. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronics packages. The previous reports, released in January of 2012 and January of 2013, presented package test data, assembly information, and reliability evaluation by thermal cycling for CGA packages with 1752, 1517, 1509, and 1272 inputs/outputs (I/Os) and 1-mm pitch. It presented the thermal cycling (-55C either 100C or 125C) test results for up to 200 cycles. This report presents up to 500 thermal cycles with quality assurance and failure analysis evaluation represented by optical photomicrographs, 2D real time X-ray images, dye-and-pry photomicrographs, and optical/scanning electron Microscopy (SEM) cross-sectional images. The report also presents assembly challenge using reflowing by either vapor phase or rework station of CGA and land grid array (LGA) versions of three high I/O packages both ceramic and plastic configuration. A new test vehicle was designed having high density interconnect (HDI) printed circuit board (PCB) with microvia-in-pad to accommodate both LGA packages as well as a large number of fine pitch ball grid arrays (BGAs). The LGAs either were assembled onto HDI PCB as an LGA or were solder paste print and reflow first to form solder dome on pads before assembly. Both plastic BGAs with 1156 I/O and ceramic LGAs were assembled. It also presented the X-ray inspection results as well as failures due to 200 thermal cycles. Lessons learned on assembly of ceramic LGAs are also presented.