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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8

Accelerated thermal and mechanical testing of CSP assemblies

Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.

Chip Scale Package CSP thermal cycle fatigue solde↗

Accelerated Thermal Cycling and Failure Mechanisms

This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.

BGA CSP CBGA thermal cycle solder joint reliabilit↗

CSP Assembly Reliability

Reviews the many factors that affect interconnect reliability of emerging chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables.

chip scale package CSP solder joint reliability th↗

Visual and x-ray inspection characteristics of eutectic and lead free assemblies

For high reliability applications, visual inspection has been the key technique for most conventional electronic package assemblies. Now, the use of x-ray technique has become an additional inspection requirement for quality control and detection of unique defects due to manufacturing of advanced electronic array packages such as ball grid array (BGAs) and chip scale packages (CSPs).

x-ray↗

Reliability of CCGA and PBGA assemblies

Area Array Packages (AAPs) with 1.27 mm pitch have been the packages of the choice for commercial applications; they are now started to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic BGA (PBGA) and CSP assemblies, because of their wide usage for commercial applications, have been extensively reported in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.

stakes↗

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗

Thermal Cycle Reliability and Failure Mechanisms of CCGA and PBGA Assemblies with and without Corner Staking

Area array packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid array (PBGA) and chip scale package assemblies, because of their wide usage for commercial applications, have been extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic products and therefore is a key factor that defines reliability.However, very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace applications. For high reliability applications, numerous AAPs are available with an identical design pattern both in ceramic and plastic packages. This paper compares assembly reliability of ceramic and plastic packages with the identical inputs/outputs(I/Os) and pattern. The ceramic package was in the form of ceramic column grid array (CCGA) with 560 I/Os peripheral array with the identical pad design as its plastic counterpart.

plastic ball grid array (PBGA)↗

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue↗

Reliability and Qualification of Hardware to Enhance the Mission Assurance of JPL/NASA Projects

Packaging Qualification and Verification (PQV) and life testing of advanced electronic packaging, mechanical assemblies (motors/actuators), and interconnect technologies (flip-chip), platinum temperature thermometer attachment processes, and various other types of hardware for Mars Exploration Rover (MER)/Mars Science Laboratory (MSL), and JUNO flight projects was performed to enhance the mission assurance. The qualification of hardware under extreme cold to hot temperatures was performed with reference to various project requirements. The flight like packages, assemblies, test coupons, and subassemblies were selected for the study to survive three times the total number of expected temperature cycles resulting from all environmental and operational exposures occurring over the life of the flight hardware including all relevant manufacturing, ground operations, and mission phases. Qualification/life testing was performed by subjecting flight-like qualification hardware to the environmental temperature extremes and assessing any structural failures, mechanical failures or degradation in electrical performance due to either overstress or thermal cycle fatigue. Experimental flight qualification test results will be described in this presentation.

PRTs↗

Chip Scale Package Implementation Challenges

The JPL-led MicrotypBGA Consortium of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

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