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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

CO2 Sensors Based on Nanocrystalline SnO2 Doped with CuO

Nanocrystalline tin oxide (SnO2) doped with copper oxide (CuO) has been found to be useful as an electrical-resistance sensory material for measuring the concentration of carbon dioxide in air. SnO2 is an n-type semiconductor that has been widely used as a sensing material for detecting such reducing gases as carbon monoxide, some of the nitrogen oxides, and hydrocarbons. Without doping, SnO2 usually does not respond to carbon dioxide and other stable gases. The discovery that the electrical resistance of CuO-doped SnO2 varies significantly with the concentration of CO2 creates opportunities for the development of relatively inexpensive CO2 sensors for detecting fires and monitoring atmospheric conditions. This discovery could also lead to research that could alter fundamental knowledge of SnO2 as a sensing material, perhaps leading to the development of SnO2-based sensing materials for measuring concentrations of oxidizing gases. Prototype CO2 sensors based on CuO-doped SnO2 have been fabricated by means of semiconductor-microfabrication and sol-gel nanomaterial-synthesis batch processes that are amendable to inexpensive implementation in mass production.

Xu, Jennifer C.↗
NASA NTRS1975

Development of a monolithic GaAs integrated optical transmitter

The paper discusses a program designed for the development of a GaAs IOC transmitter consisting of a monolithic surface laser whose output is coupled into patterned channel waveguides. Modulation and switching of the radiation occur in the waveguide circuit and are controlled separately. These structures are to be fabricated monolithically on a single semiconductor chip with each device amenable to integrated low-cost manufacture. The waveguide outputs of the IOC transmitter will be coupled to single mode optical fibers which form a transmission cable. The properties of the semiconductors (Ga,Al)As and (Ga,In)As permit performance of each of the basic functions included in the device considered. The concept of monolithic nondiscrete GaAs diode lasers is examined along with optical stripline channel waveguides and electro-optic channel waveguide modulators and switches.

Blum, F. A.↗
NASA NTRS1979

Modelling switching-time effects in high-frequency power conditioning networks

Power transistor networks which switch large currents in highly inductive environments are beginning to find application in the hundred kilohertz switching frequency range. Recent developments in the fabrication of metal-oxide-semiconductor field-effect transistors in the power device category have enhanced the movement toward higher switching frequencies. Models for switching devices and of the circuits in which they are imbedded are required to properly characterize the mechanisms responsible for turning on and turning off effects. Easily interpreted results in the form of oscilloscope-like plots assist in understanding the effects of parametric studies using topology oriented computer-aided analysis methods.

Owen, H. A.↗
NASA NTRS1983

Diffraction coupled phase-locked semiconductor laser array

A new monolithic, diffraction coupled phase-locked semiconductor laser array has been fabricated. Stable narrow far-field patterns (approximately 3 deg) and peak power levels of 1 W have been obtained for 100-micron-wide devices with threshold currents as low as 250 mA. Such devices may be useful in applications where high power levels and stable radiation patterns are needed.

Katz, J.↗
NASA NTRS1983

Phase-locked semiconductor laser array with separate contacts

A new monolithic phase-locked semiconductor laser array has been fabricated. Employing two-level metallization, each of the eight elements in the array has a separate contact, thus making it possible to compensate for device nonuniformities and control the near-field and far-field patterns. Threshold currents are approximately 60 mA for each 5-micron-wide laser in the array. Phase locking has been observed via the narrowing of the far-field pattern. Experimental results are compared to those obtained from the same arrays operated with all the lasers connected in parallel.

Katz, J.↗
NASA NTRS1986

Inversion layer MOS solar cells

Inversion layer (IL) Metal Oxide Semiconductor (MOS) solar cells were fabricated. The fabrication technique and problems are discussed. A plan for modeling IL cells is presented. Future work in this area is addressed.

Ho, Fat Duen↗
NASA NTRS1991

High temperature superconductive microwave technology for space applications

Progress being made on space application technology research on film fabrication, passive microwave circuits, and semiconductor devices for cryogenic circuits is reviewed. Achievements in YBCO and TCBCO films are addressed along with circuit evaluations of microstrip resonators, phase shifters, microstrip filters, dielectric resonator filters, and superconducting antennas.

Leonard, R. F.↗
NASA NTRS1995

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗
NASA NTRS1995

Controlled Thin-Film Growth Of Silicon Carbide Polytypes

Improved deposition process to grows thin layers of silicon carbide having chosen crystalline structures. Process incorporated into sequences of deposition and etching steps used to fabricate silicon-carbide-based semiconductor devices. Important advance because silicon carbide emerging as superior semiconductor for devices operating under conditions of high power, high temperature, and/or high frequency. Furthermore, various crystalline structures of SiC have different electronic properties, each suited to specific application.

Powell, J. Anthony↗
NASA NTRS2004

High-Temperature Probe Station Developed to Characterize Microwave Devices Through 500 C

A photograph and a block diagram of the high-temperature probe station are shown. The system consists of the ceramic heater mounted on a NASA shuttle tile insulator, a direct current power supply, a personal-computer-based data acquisition and temperature controller, microwave probes, a microscope, and a network analyzer. The ability to perform microwave tests at high temperatures is becoming necessary. There is now a need for sensors and communication circuits that can operate at 500 C and above for aircraft engine development and monitoring during flight. To address this need, researchers have fabricated devices using wide bandgap semiconductors such as SiC with targeted operating temperatures of 500 to 600 C. However, the microwave properties of these devices often change drastically with temperature, so any designs that are intended to be used in such an environment must be characterized at high temperatures. For some reliability, lifetime, and direct-current testing, the device under test can be packaged and characterized in an oven. However, for RF and microwave measurements, it is usually not possible to establish a calibrated reference plane at the device terminals within a package. In addition, the characteristics of the package would vary over a 500 C temperature range, and this would have to be accounted for when the data were analyzed. A high temperature probe station allows circuits and devices to be characterized through on wafer measurements across a broad temperature range with known reference plane. The conventional, commercially available thermal wafer-probe stations that are used to evaluate microwave devices across a controlled temperature range have a typical upper limit of 200 C. Standalone thermal heating chucks are available with an extended upper temperature range of 300 to 400 C. To effectively characterize devices at temperatures up to and surpassing 500 C, Glenn researchers developed a custom probe station. In the past, custom probe stations have been developed to test devices under other extreme environments, such as cryogenic temperatures as low as 37 K. Similarly, this custom probe station was specifically modified for high-temperature use. It allows devices to be measured quickly and flexibly, without the use of wire bonds and test fixtures. The probe station is shown making scattering parameter measurements from 1 to 50 GHz with a Hewlett-Packard 8510C Network Analyzer. There is a half-wafer of silicon directly on top of the heater to provide a uniform heated platform for our sample. A quarter wafer of silicon carbide forms the substrate for our test circuit of several transmission lines.

Downey, Alan N.↗
NASA NTRS1998

Advanced thermoelectric materials with enhanced crystal lattice structure and methods of preparation

New skutterudite phases including Ru.sub.0.5 Pd.sub.0.5 Sb.sub.3, RuSb.sub.2 Te, and FeSb.sub.2 Te, have been prepared having desirable thermoelectric properties. In addition, a novel thermoelectric device has been prepared using skutterudite phase Fe.sub.0.5 Ni.sub.0.5 Sb.sub.3. The skutterudite-type crystal lattice structure of these semiconductor compounds and their enhanced thermoelectric properties results in semiconductor materials which may be used in the fabrication of thermoelectric elements to substantially improve the efficiency of the resulting thermoelectric device. Semiconductor materials having the desired skutterudite-type crystal lattice structure may be prepared in accordance with the present invention by using powder metallurgy techniques. Measurements of electrical and thermal transport properties of selected semiconductor materials prepared in accordance with the present invention, demonstrated high Hall mobilities and good Seebeck coefficients. These materials have low thermal conductivity and relatively low electrical resistivity, and are good candidates for low temperature thermoelectric applications.

Fleurial, Jean-Pierre↗
NASA NTRS1999

Silica Integrated Optical Circuits Based on Glass Photosensitivity

Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

Abushagur, Mustafa A. G.↗
NASA NTRS1990

End-of-fabrication CMOS process monitor

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.↗
NASA NTRS1999

Evanescent Microwave Probes on High-Resistivity Silicon and its Application in Characterization of Semiconductors

In this article we report the design, fabrication, and characterization of very high quality factor 10 GHz microstrip resonators on high-resistivity (high-rho) silicon substrates. Our experiments show that an external quality factor of over 13 000 can be achieved on microstripline resonators on high-rho silicon substrates. Such a high Q factor enables integration of arrays of previously reported evanescent microwave probe (EMP) on silicon cantilever beams. We also demonstrate that electron-hole pair recombination and generation lifetimes of silicon can be conveniently measured by illuminating the resonator using a pulsed light. Alternatively, the EMP was also used to nondestructively monitor excess carrier generation and recombination process in a semiconductor placed near the two-dimensional resonator.

Tabib-Azar, M.↗
NASA NTRS2018

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗
NASA NTRS1979

All-ion-implantation process for integrated circuits

Simpler than diffusion fabrication, ion bombardment produces complementary-metal-oxide-semiconductor / silicon-on-sapphire (CMOS/SOS) circuits that are one-third faster. Ion implantation simplifies the integrated circuit fabrication procedure and produces circuits with uniform characteristics.

Woo, D. S.↗
NASA NTRS2005

In Situ Electrochemical Deposition of Microscopic Wires

A method of fabrication of wires having micron and submicron dimensions is built around electrochemical deposition of the wires in their final positions between electrodes in integrated circuits or other devices in which the wires are to be used. Heretofore, nanowires have been fabricated by a variety of techniques characterized by low degrees of controllability and low throughput rates, and it has been necessary to align and electrically connect the wires in their final positions by use of sophisticated equipment in expensive and tedious post-growth assembly processes. The present method is more economical, offers higher yields, enables control of wire widths, and eliminates the need for post-growth assembly. The wires fabricated by this method could be used as simple electrical conductors or as transducers in sensors. Depending upon electrodeposition conditions and the compositions of the electroplating solutions in specific applications, the wires could be made of metals, alloys, metal oxides, semiconductors, or electrically conductive polymers. In this method, one uses fabrication processes that are standard in the semiconductor industry. These include cleaning, dry etching, low-pressure chemical vapor deposition, lithography, dielectric deposition, electron-beam lithography, and metallization processes as well as the electrochemical deposition process used to form the wires. In a typical case of fabrication of a circuit that includes electrodes between which microscopic wires are to be formed on a silicon substrate, the fabrication processes follow a standard sequence until just before the fabrication of the microscopic wires. Then, by use of a thermal SiO-deposition technique, the electrodes and the substrate surface areas in the gaps between them are covered with SiO. Next, the SiO is electron-beam patterned, then reactive-ion etched to form channels having specified widths (typically about 1 m or less) that define the widths of the wires to be formed. Drops of an electroplating solution are placed on the substrate in the regions containing the channels thus formed, then the wires are electrodeposited from the solution onto the exposed portions of the electrodes and into the channels. The electrodeposition is a room-temperature, atmospheric-pressure process. The figure shows an example of palladium wires that were electrodeposited into 1-mm-wide channels between gold electrodes.

Yun, Minhee↗