An algorithm and a program for generation of test patterns for sequential circuits
Test pattern generation algorithm and program for failure detection in asynchronous sequential logic circuits, using combinational method
Putzolu, G. R.↗
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System and method for large-scale PCB production including continuous selective adhesion
A method for the large-scale production of PCBs including a continuous selective adhesion process for creating printed circuit traces providing input to a production line. A roll of printed circuit traces is produced using rolls of flexible substrate, conductive layer, and conductive layer support by applying adhesive between the rolls of flexible substrate and conductive layer, bringing the rolls together, transferring a circuit pattern onto the flexible substrate, curing the adhesive through non-opaque areas of the circuit pattern, and separating the non-bonded areas. The resulting printed circuit traces are applied from the roll to mounts, and circuit components are applied from a roll to the traces as the mounts move along the line. Additional rolls of printed circuit traces and circuit components may be incorporated, and multi-layer PCBs may be produced. As part of the production line, the finished PCBs may be applied to flat or contoured products.
Hatch, Jonathan Douglas↗
General technique for the integration of MIC/MMIC'S with waveguides
A technique for packaging and integrating of a microwave integrated circuit (MIC) or monolithic microwave integrated circuit (MMIC) with a waveguide uses a printed conductive circuit pattern on a dielectric substrate to transform impedance and mode of propagation between the MIC/MMIC and the waveguide. The virtually coplanar circuit pattern lies on an equipotential surface within the waveguide and therefore makes possible single or dual polarized mode structures.
Geller, Bernard D.↗
Process for making a multilayer interconnect system
A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.
Zachry, Clyde L.↗
Screened circuit fabrication equipment.
Stencil screening methods for printing integrated circuit patterns for resistors, capacitors, etc, discussing automation possibilities
INTEGRATED CIRCUIT↗
Innovative, Inexpensive Etching Technique Developed for Polymer Electro- Optical Structures
Electro-optic, polymer-based integrated optic devices for high-speed communication and computing applications offer potentially significant advantages over conventional inorganic electro-optic crystals. One key area of integrated optical technology--primary processing and fabrication--may particularly benefit from the use of polymer materials. However, as efforts concentrate on the miniaturization of electro-integrated circuit pattern geometries, the ability to etch fine features and smoothly sloped sidewalls is essential to make polymers useful for electro-integrated circuit applications. There are many existing processes available to etch polymer materials, but they all yield nearly vertical sidewalls. Vertical sidewalls are too difficult to reliably cover with a metal layer, and incomplete metalization degrades microwave performance, particularly at high frequency. However, obtaining a very sloped sidewall greatly improves the deposition of metal on the sidewall, leading to low-loss characteristics, which are essential to integrating these devices in highspeed electro-optic modulators. The NASA Lewis Research Center has developed in-house an inexpensive etching technique that uses a photolithography method followed by a simple, wet chemical etching process to etch through polymer layers. In addition to being simpler and inexpensive, this process can be used to fabricate smoothly sloped sidewalls by using a commercial none rodible mask: Spin-On-Glass. A commercial transparent material, Spin-On-Glass, uses processes and equipment similar to that for photoresist techniques.
Nguyen, Hung D.↗
Controlled wetting and spreading of metals on substrates using porous interlayers and related articles
The disclosure generally relates to a method of creating patterned metallic circuits (e.g., silver circuits) on a substrate (e.g., a ceramic substrate). A porous metal interlayer (e.g., porous nickel) is applied to the substrate to improve wetting and adhesion of the patterned metal circuit material to the substrate. The substrate is heated to a temperature sufficient to melt the patterned metal circuit material but not the porous metal interlayer. Spreading of molten metal circuit material on the substrate is controlled by the porous metal interlayer, which can itself be patterned, such as having a defined circuit pattern. Thick-film silver or other metal circuits can be custom designed in complicated shapes for high temperature/high power applications. The materials designated for the circuit design allows for a low-cost method of generating silver circuits other metal circuits on a ceramic substrate.
Nicholas, Jason Dale↗
Associative Pattern Recognition In Analog VLSI Circuits
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Tawel, Raoul↗
Test pattern generation for ILA sequential circuits
An efficient method of generating test patterns for sequential machines implemented using one-dimensional, unilateral, iterative logic arrays (ILA's) of BTS pass transistor networks is presented. Based on a transistor level fault model, the method affords a unique opportunity for real-time fault detection with improved fault coverage. The resulting test sets are shown to be equivalent to those obtained using conventional gate level models, thus eliminating the need for additional test patterns. The proposed method advances the simplicity and ease of the test pattern generation for a special class of sequential circuitry.
Feng, YU↗
DALG: A program for test pattern generation in combinational logical circuits
A user's manual for a computer program DALG which generates test patterns for detecting faults in combinational logic circuits containing up to 200 logical gates is presented. The gates may be of logical types AND, OR, NAND, NOR, NOT, or Exclusive OR is presented. The faults may be any one gate or input struck at a fixed value (0 or 1). In addition to test pattern generation DALG will also determine whether or not the given test pattern will detect given faults in a circuit. Sample problems are given along with input data sheets and printed output to illustrate the capabilities of the program.
Source record↗
Five-Segment Interconnection For Electromigration Tests
Proposed integrated-circuit conductive pattern intended for use in electromigration lifetime testing of interconnection lines of integrated circuits. Designed for collection of statistics on electromigration from smallest possible area. Includes 5 interconnection segments with Kelvin voltage taps, with total of 12 contact pads, and provides for simultaneous measurements on all of segments. Attempts to minimize thermal gradients within each segment and conforms to guidelines on electromigration test structures promulgated by National Institute of Standards and Technology (NIST).
Hannaman, David J.↗
Antenna system
An antenna system comprises a substrate, an antenna positioned on the substrate, and a circuit component positioned on the substrate. The antenna is positioned on a first surface of the substrate and operable to emit a radiation pattern. The circuit component is positioned on the substrate in a null region of the radiation pattern. The thickness of portions of the substrate are modified to achieve a desired performance characteristic of the antenna.
Byers, Kyle J.↗
Spatiotemporal pattern detection, generation, and computation with circuits
Abstract Implementations of neurons, delays, and synapse circuits are presented with simulations. These neural elements are used to create two small spiking neural networks, the Rate-Window and Order-Biased clusters, which are capable of detecting simple two-spike spatiotemporal patterns. A simple pattern detecting network (SPDN) is created by combining the Rate-Window and Order-Biased clusters, where clusters are small spiking neural networks, and its simple pattern detection ability is demonstrated in simulation. The SPDN is used to implement a complex pattern detecting network (CPDN) and its complex pattern detection ability is demonstrated in simulation. Methods for generating arbitrary spatiotemporal patterns are presented. The CPDN and spatiotemporal pattern generation methods are then used to implement a novel spatiotemporal computing paradigm based on detecting and responding to spatiotemporal symbols. A simulation of a spatiotemporal half adder is presented to demonstrate the computing paradigm.
97 - MATHEMATICS AND COMPUTING↗
Carbon Nanotube-Based Structural Health Monitoring Sensors
Carbon nanotube (CNT)-based sensors for structural health monitoring (SHM) can be embedded in structures of all geometries to monitor conditions both inside and at the surface of the structure to continuously sense changes. These CNTs can be manipulated into specific orientations to create small, powerful, and flexible sensors. One of the sensors is a highly flexible sensor for crack growth detection and strain field mapping that features a very dense and highly ordered array of single-walled CNTs. CNT structural health sensors can be mass-produced, are inexpensive, can be packaged in small sizes (0.5 micron(sup 2)), require less power than electronic or piezoelectric transducers, and produce less waste heat per square centimeter than electronic or piezoelectric transducers. Chemically functionalized lithographic patterns are used to deposit and align the CNTs onto metallic electrodes. This method consistently produces aligned CNTs in the defined locations. Using photo- and electron-beam lithography, simple Cr/Au thin-film circuits are patterned onto oxidized silicon substrates. The samples are then re-patterned with a CNT-attracting, self-assembled monolayer of 3-aminopropyltriethoxysilane (APTES) to delineate the desired CNT locations between electrodes. During the deposition of the solution-suspended single- wall CNTs, the application of an electric field to the metallic contacts causes alignment of the CNTs along the field direction. This innovation is a prime candidate for smart skin technologies with applications ranging from military, to aerospace, to private industry.
Wincheski, Russell↗
Ciliary localization of a light-activated neuronal GPCR shapes behavior
Many neurons in the central nervous system produce a single primary cilium that serves as a specialized signaling organelle. Several neuromodulatory G-protein-coupled receptors (GPCRs) localize to primary cilia in neurons, although it is not understood how GPCR signaling from the cilium impacts circuit function and behavior. We find that the vertebrate ancient long opsin A (VALopA), a Gi-coupled GPCR extraretinal opsin, targets to cilia of zebrafish spinal neurons. In the developing 1-d-old zebrafish, brief light activation of VALopA in neurons of the central pattern generator circuit for locomotion leads to sustained inhibition of coiling, the earliest form of locomotion. We find that a related extraretinal opsin, VALopB, is also Gi-coupled, but is not targeted to cilia. Light-induced activation of VALopB also suppresses coiling, but with faster kinetics. We identify the ciliary targeting domains of VALopA. Retargeting of both opsins shows that the locomotory response is prolonged and amplified when signaling occurs in the cilium. We propose that ciliary localization provides a mechanism for enhancing GPCR signaling in central neurons.
59 BASIC BIOLOGICAL SCIENCES↗
Banning artwork program user's manual
A manual containing computer programs for designing circuits is presented. A description of the pattern library, the plotter used to draw the circuit patterns, and program control cards is given. Sample printouts and cards are shown.
Taylor, J. F.↗
Patterned nickel interlayers for enhanced silver wetting, spreading and adhesion on ceramic substrates
Not Available
36 MATERIALS SCIENCE↗
Porphene and porphite as porphyrin analogs of graphene and graphite
Two-dimensional materials have unusual properties and promise applications in nanoelectronics, spintronics, photonics, (electro)catalysis, separations, and elsewhere. Most are inorganic and their properties are difficult to tune. Here we report the preparation of Zn porphene, a member of the previously only hypothetical organic metalloporphene family. Similar to graphene, these also are fully conjugated two-dimensional polymers, but are composed of fused metalloporphyrin rings. Zn porphene is synthesized on water surface by two-dimensional oxidative polymerization of a Langmuir layer of Zn porphyrin with K 2 IrCl 6 , reminiscent of known one-dimensional polymerization of pyrroles. It is transferable to other substrates and bridges μm-sized pits. Contrary to previous theoretical predictions of metallic conductivity, it is a p-type semiconductor due to a predicted Peierls distortion of its unit cell from square to rectangular, analogous to the appearance of bond-length alternation in antiaromatic molecules. The observed reversible insertion of various metal ions, possibly carrying a fifth or sixth ligand, promises tunability and even patterning of circuits on an atomic canvas without removing any π centers from conjugation.
36 MATERIALS SCIENCE↗