An algorithm and a program for generation of test patterns for sequential circuits
Test pattern generation algorithm and program for failure detection in asynchronous sequential logic circuits, using combinational method
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Test pattern generation algorithm and program for failure detection in asynchronous sequential logic circuits, using combinational method
A technique for packaging and integrating of a microwave integrated circuit (MIC) or monolithic microwave integrated circuit (MMIC) with a waveguide uses a printed conductive circuit pattern on a dielectric substrate to transform impedance and mode of propagation between the MIC/MMIC and the waveguide. The virtually coplanar circuit pattern lies on an equipotential surface within the waveguide and therefore makes possible single or dual polarized mode structures.
A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.
Stencil screening methods for printing integrated circuit patterns for resistors, capacitors, etc, discussing automation possibilities
Electro-optic, polymer-based integrated optic devices for high-speed communication and computing applications offer potentially significant advantages over conventional inorganic electro-optic crystals. One key area of integrated optical technology--primary processing and fabrication--may particularly benefit from the use of polymer materials. However, as efforts concentrate on the miniaturization of electro-integrated circuit pattern geometries, the ability to etch fine features and smoothly sloped sidewalls is essential to make polymers useful for electro-integrated circuit applications. There are many existing processes available to etch polymer materials, but they all yield nearly vertical sidewalls. Vertical sidewalls are too difficult to reliably cover with a metal layer, and incomplete metalization degrades microwave performance, particularly at high frequency. However, obtaining a very sloped sidewall greatly improves the deposition of metal on the sidewall, leading to low-loss characteristics, which are essential to integrating these devices in highspeed electro-optic modulators. The NASA Lewis Research Center has developed in-house an inexpensive etching technique that uses a photolithography method followed by a simple, wet chemical etching process to etch through polymer layers. In addition to being simpler and inexpensive, this process can be used to fabricate smoothly sloped sidewalls by using a commercial none rodible mask: Spin-On-Glass. A commercial transparent material, Spin-On-Glass, uses processes and equipment similar to that for photoresist techniques.
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
An efficient method of generating test patterns for sequential machines implemented using one-dimensional, unilateral, iterative logic arrays (ILA's) of BTS pass transistor networks is presented. Based on a transistor level fault model, the method affords a unique opportunity for real-time fault detection with improved fault coverage. The resulting test sets are shown to be equivalent to those obtained using conventional gate level models, thus eliminating the need for additional test patterns. The proposed method advances the simplicity and ease of the test pattern generation for a special class of sequential circuitry.
A user's manual for a computer program DALG which generates test patterns for detecting faults in combinational logic circuits containing up to 200 logical gates is presented. The gates may be of logical types AND, OR, NAND, NOR, NOT, or Exclusive OR is presented. The faults may be any one gate or input struck at a fixed value (0 or 1). In addition to test pattern generation DALG will also determine whether or not the given test pattern will detect given faults in a circuit. Sample problems are given along with input data sheets and printed output to illustrate the capabilities of the program.
Proposed integrated-circuit conductive pattern intended for use in electromigration lifetime testing of interconnection lines of integrated circuits. Designed for collection of statistics on electromigration from smallest possible area. Includes 5 interconnection segments with Kelvin voltage taps, with total of 12 contact pads, and provides for simultaneous measurements on all of segments. Attempts to minimize thermal gradients within each segment and conforms to guidelines on electromigration test structures promulgated by National Institute of Standards and Technology (NIST).
Carbon nanotube (CNT)-based sensors for structural health monitoring (SHM) can be embedded in structures of all geometries to monitor conditions both inside and at the surface of the structure to continuously sense changes. These CNTs can be manipulated into specific orientations to create small, powerful, and flexible sensors. One of the sensors is a highly flexible sensor for crack growth detection and strain field mapping that features a very dense and highly ordered array of single-walled CNTs. CNT structural health sensors can be mass-produced, are inexpensive, can be packaged in small sizes (0.5 micron(sup 2)), require less power than electronic or piezoelectric transducers, and produce less waste heat per square centimeter than electronic or piezoelectric transducers. Chemically functionalized lithographic patterns are used to deposit and align the CNTs onto metallic electrodes. This method consistently produces aligned CNTs in the defined locations. Using photo- and electron-beam lithography, simple Cr/Au thin-film circuits are patterned onto oxidized silicon substrates. The samples are then re-patterned with a CNT-attracting, self-assembled monolayer of 3-aminopropyltriethoxysilane (APTES) to delineate the desired CNT locations between electrodes. During the deposition of the solution-suspended single- wall CNTs, the application of an electric field to the metallic contacts causes alignment of the CNTs along the field direction. This innovation is a prime candidate for smart skin technologies with applications ranging from military, to aerospace, to private industry.
A manual containing computer programs for designing circuits is presented. A description of the pattern library, the plotter used to draw the circuit patterns, and program control cards is given. Sample printouts and cards are shown.
Spring-loaded optical mounts maintain flatness and alinement of rigid, framed, or pellicle beam splitters over wide temperature range, despite differences in thermal expansion amoung materials. Mounts permit optical adjustments at ambient temperature even though optical system operated subsequently within few degrees of absolute zero. Mounts useful as holders for integrated-circuit master patterns, survey targets, vibrating membranes, noise- or pressure-sensing membranes, osmosis filters, and fuel-cell elements.
Quick visual inspection identifies out-of-place layers. Small copper pads or other labels on layers present regular pattern if multilayer circuit board properly assembled and irregular pattern if one or more layers in wrong place. New method faster, cheaper, and more reliable than earlier methods.
Nickel-plated device, with machined recesses matching the multipin pattern of particular circuit module, facilitates repairs to electronic systems and reduces chance of damage to adjacent components. Nickel-plating reduces oxidation and scaling. Recesses retain sufficient amount of molten solder to uniformly wet pins for simultaneous heating and extraction.
The development of high T sub c superconducting thin films on various microwave substrates is of major interest in space electronic systems. Thin films of YBa2Cu3O(7-Delta) were formed on SrTiO3, MgO, ZrO2 coated Al2O3, and LaAlO3 substrates by multi-layer sequential evaporation and subsequent annealing in oxygen. The technique allows controlled deposition of Cu, BaF2 and Y layers, as well as the ZrO buffer layers, to achieve reproducibility for microwave circuit fabrication. The three layer structure of Cu/BaF2/Y is repeated a minimum of four times. The films were annealed in an ambient of oxygen bubbled through water at temperatures between 850 C and 900 C followed by slow cooling (-2 C/minute) to 450 C, a low temperature anneal, and slow cooling to room temperature. Annealing times ranged from 15 minutes to 5 hrs. at high temperature and 0 to 6 hr. at 450 C. Silver contacts for four probe electrical measurements were formed by evaporation followed with an anneal at 500 C. The films were characterized by resistance-temperature measurements, energy dispersive X-ray spectroscopy, X-ray diffraction, and scanning electron microscopy. Critical transition temperatures ranged from 30 K to 87 K as a function of the substrate, composition of the film, thicknesses of the layers, and annealing conditions. Microwave ring resonator circuits were also patterned on these MgO and LaAlO3 substrates.
Integrated-circuit conductive test pattern intended to provide data on effects of design widths and design spacings upon actual widths of conductive lines. Provides for electrical measurements both on lines of unknown width and on features having known dimensions. Data from measurements on five bridges used to determine four parameters of mathematical model describing system. In principle, pattern determines effects of width and spacing and interaction between them.
New facilities and test techniques afford research aerodynamicists many opportunities to investigate complex aerodynamic phenomena. For example, NASA Langley Research Center's National Transonic Facility (NTF) can hold Mach number, Reynolds number, dynamic pressure, stagnation temperature and stagnation pressure constant during testing. This is important because the wing twist associated with model construction may mask important Reynolds number effects associated with the flight vehicle. Beyond this, the NTF's ability to vary Reynolds number allows for important research into the study of boundary layer transition. The capabilities of facilities such as the NTF coupled with test techniques such as temperature sensitive paint yield data that can be applied not only to vehicle design but also to validation of computational methods. Development of Luminescent Paint Technology for acquiring pressure and temperature measurements began in the mid-1980s. While pressure sensitive luminescent paints (PSP) were being developed to acquire data for aerodynamic performance and loads, temperature sensitive luminescent paints (TSP) have been used for a much broader range of applications. For example, TSP has been used to acquire surface temperature data to determine the heating due to rotating parts in various types of mechanical systems. It has been used to determine the heating pattern(s) on circuit boards. And, it has been used in boundary layer analysis and applied to the validation of full-scale flight performance predictions. That is, data acquired on the same model can be used to develop trends from off design to full scale flight Reynolds number, e.g. to show the progression of boundary layer transition. A discussion of issues related to successfully setting-up TSP tests and using TSP systems for boundary layer studies is included in this paper, as well as results from a variety of TSP tests. TSP images included in this paper are all grey-scale so that similar to pictures from sublimating chemical tests areas of laminar flow appear "lighter," or white, and areas of turbulent flow appear "darker."
Metal interconnection pattern deposited on integrated circuit or solar cell economically by thermal decomposition of metallo-organic compound. In proposed process beam from laser or quartz lamp swept over substrate in required metalization pattern; wherever beam impinges on substrate, radiant heat decomposes compound, depositing metal. Process requires less costly equipment and less time than conventional metalization. Process readily adaptable to very-large-scale integrated (VLSI) circuits.