Fragmentation Analysis of High-Energy Heavy Ion Beams for Single-Event Effects Testing at NSRL
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Various papers on nuclear and space radiation effects are presented. The general topics addressed include: basic mechanisms of radiation effects, single-event phenomena, temperature and field effects, modeling and characterization of radiation effects, IC radiation effects and hardening, and EMP/SGEMP/IEMP phenomena. Also considered are: dosimetry/energy-dependent effects, sensors in and for radiation environments, spacecraft charging and space radiation effects, radiation effects and devices, radiation effects on isolation technologies, and hardness assurance and testing techniques.
Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.
This paper presents the results of reliability life testing performed on commercial electronic devices that experienced non-destructive single-event latch-up (SEL) during heavy-ion testing.
Cosmic-ray heavy ions have become a concern in space radiation effects analyses. Heavy ions rapidly deposit energy and create dense ionization trails as they traverse materials. Collection of the free charge disrupts the operation of microelectronic circuits. This effect, called the single-event upset, can cause a loss of digital data. Passage of high linear energy transfer particles through the eyes has been observed by Apollo astronauts. These heavy ions have great radiobiological effectiveness and are the primary risk factor for leukemia induction on a manned Mars mission. Models of the transport of heavy cosmic-ray nuclei through materials depend heavily on our understanding of the cosmic-ray environment, nuclear spallation cross sections, and computer transport codes. Our group has initiated and pursued the development of a full capability for modeling these transport processes. A recent review of this ongoing effort is presented in Ref. 5. In this paper, we discuss transport methods and present new results comparing the attenuation of cosmic rays in various materials.
The present conference on the effects of nuclear and space radiation on electronic hardware gives attention to topics in the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, electronic device radiation hardness assurance, SOI/SOS radiation effects, spacecraft charging and space radiation, IC radiation effects and hardening, single-event upset (SEU) phenomena and hardening, and EMP/SGEMP/IEMP phenomena. Specific treatments encompass the generation of interface states by ionizing radiation in very thin MOS oxides, the microdosimetry of meson energy deposited on 1-micron sites in Si, total dose radiation and engineering studies, plasma interactions with biased concentrator solar cells, the transient imprint memory effect in MOS memories, mechanisms leading to SEU, and the vaporization and breakdown of thin columns of water.
The effects of nuclear and space radiation on the performance of electronic devices are discussed in reviews and reports of recent investigations. Topics addressed include the basic mechanisms of radiation effects, dosimetry and energy-dependent effects, sensors in and for radiation environments, EMP/SGEMP/IEMP phenomena, radiation effects on isolation technologies, and spacecraft charging and space radiation effects. Consideration is given to device radiation effects and hardening, hardness assurance and testing techniques, IC radiation effects and hardening, and single-event phenomena.
Radiation effects on electronic systems and devices (particularly spacecraft systems) are examined with attention given to such topics as radiation transport, energy deposition, and charge collection; single-event phenomena; basic mechanisms of radiation effects in structures and materials; and EMP phenomena. Also considered are radiation effects in integrated circuits, spacecraft charging and space radiation effects, hardness assurance for devices and systems, and SGEMP/IEMP phenomena.
The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.
A method for generating noise contours more rapidly and more simply than previously used programs is discussed. The method gives the area, the noise contour, and its extremities for an arbitrarily complex flight path for both takeoffs and landings with relative ease. The analysis reveals the fundamental nature of the contours and how the various factors that influence its size and shape enter into the analysis. It is noted that the effects of ground attenuation and shielding are omitted as they are important only on the initial portion of flight and are highly dependent upon aircraft configuration. However, the analysis shows that these effects could be included. It is emphasized the the single-event contour is an obvious choice for purposes of minimizing noise impact.
Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.
The Galileo probe will be subject to radiation fields and energetic particle bombardment during its outward bound journey and in orbit around Jupiter and its moons. To avoid the occurrence and propagation of effects of single event upset (SEU) bit state changes induced by the bombardments attempts were made to harden the Galileo electronics against SEUs. The hazards are especially acute for Schottky diode and low-power Schottky TTL parts. The preventive action options which were scheduled are reviewed, noting the selection of CMOS chips as replacements for SEU-susceptible devices. The simulation and risk assessment that were performed to evaluate the potential success of the replacements are summarized, with emphasis on the data employed to ensure the accuracy of the assessments and the predicted effects of SEUs in the various Galileo subsystems.
Single-event upset (SEU) cross sections are reduced in 176-layer charge trap (CT) 3-D nand devices under proton irradiation when multiple write operations are applied sequentially without the typical erase-before-write. Here, this effect is observed for multiple data patterns and in both single-level cell (SLC) and triple-level cell (TLC) operating modes. SEU cross section calculation methodologies are discussed for highly scaled 3-D devices both with and without the application of rewrites, and potential implications for long-term endurance effects are proposed.
Topics discussed include radiation effects in devices; the basic mechanisms of radiation effects in structures and materials; radiation effects in integrated circuits; spacecraft charging and space radiation effects; hardness assurance for devices and systems; and radiation transport, energy deposition and charge collection. Papers are presented on the mechanisms of small instabilities in irradiated MOS transistors, on the radiation effects on oxynitride gate dielectrics, on the discharge characteristics of a simulated solar cell array, and on latchup in CMOS devices from heavy ions. Attention is also given to proton upsets in orbit, to the modeling of single-event upset in bipolar integrated circuits, to high-resolution studies of the electrical breakdown of soil, and to a finite-difference solution of Maxwell's equations in generalized nonorthogonal coordinates.
Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.
Low-power devices susceptible to cosmic-ray particles. Five MSI device technologies, including TTL, low power TTL, Schottky, CMOS, and low-power Schottky, subjected to 120-MeV krypton-ion beam from cyclotron and monitored for single-event upset. Results find terrestrial application for radiation hardening of electronic devices and systems.
A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.
Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .