TCAD simulations of humidity-induced breakdown of silicon sensors
Not Available
Ninca, I-S. (ORCID:0000000181588966)↗
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Analysis of MOS capacitor with p layer with TCAD simulation
Not Available
Unno, Y. (ORCID:0000000241708537)↗
TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET
We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.
COTS↗
Dopant Optimization of Donors in Semiconductor Opening Switches to Eliminate Prepulse
Semiconductor opening switches are solid-state devices capable of delivering nanosecond, hundreds of kilovolts pulses by interrupting kiloamps of current. The interruption of the current occurs in a moderately doped p-region when a high electric field region (HFR) is formed. The HFR occurs because the reverse pumping current cannot be supported by the saturation velocity and majority carrier concentration of the doping level. However, the donor profile also significantly affects the pulse performance. A secondary prepulse occurs if a secondary HFR is formed at the interface of the background n-doping and N+ doping (X n ) . By moving the location of X n deeper into the diode, the effect of the prepulse is reduced. This article investigates the effect of the donor doping profile on the performance metrics of semiconductor opening switches through technology computer-aided design (TCAD) simulations and experimental results. Through a SILVACO TCAD optimization, we designed a P + /p/n - base/n/N + where the intersection of the moderate p-region and intrinsic n-base region (X p ) is at 160 μm and X n is at 220 μm. This profile is fabricated via silicon epitaxy. Experimentally, it is shown that a deep X n (220 μm) compared with a shallow X n (300 μm) reduces the rise time by >5× . In addition, the magnitude of current density during interruption affects the prepulse foot and pulse shape. At lower current densities without the graded donor profile, high peak voltages are not achieved. Comparing the experimental results to the TCAD simulations shows that the model is predictive under high-current densities in the semiconductor opening switch (SOS) regime.
nanosecond pulse power↗
Diffused trenches for high fill-factor Low-Gain Avalanche Diodes
Low-Gain Avalanche Diodes (LGADs) are a class of silicon detectors that have been specifically designed for the fast detection of minimum ionizing particles (mips) in High-Energy Physics experiments. While they provide timing resolution on the order of a few tens of picoseconds, they cannot achieve high spatial resolution due to the intrinsic characteristics of their structures. Thus, active R&D is on-going to develop detectors based on LGADs to improve their spatial resolution while maintaining the timing performance of the LGADs. Such devices are, for example, AC-coupled LGADs and Deep-Junction LGADs. Another device option is the Trench-Isolated LGAD (TI LGAD), where trenches etched at the periphery of the pixels isolate them while providing a high fill-factor. Here, in this paper, we present a variation of this latter approach, demonstrating its feasibility by means of 2-dimensional TCAD simulations.
47 OTHER INSTRUMENTATION↗
Vertical van der Waals heterojunction diodes comprising 2D semiconductors on 3D β-Ga 2 O 3
Wide bandgap semiconductors such as gallium oxide (Ga 2 O 3 ) have attracted much attention for their use in next-generation high-power electronics. Although single-crystal Ga 2 O 3 substrates can be routinely grown from melt along various orientations, the influence of such orientations has been seldom reported. Further, making rectifying p–n diodes from Ga 2 O 3 has been difficult due to lack of p-type doping. In this study, we fabricated and optimized 2D/3D vertical diodes on β-Ga 2 O 3 by varying the following three factors: substrate planar orientation, choice of 2D material and metal contacts. Furthermore, the quality of our devices was validated using high-temperature dependent measurements, atomic-force microscopy (AFM) techniques and technology computer-aided design (TCAD) simulations. Our findings suggest that 2D/3D β-Ga 2 O 3 vertical heterojunctions are optimized by substrate planar orientation (–201), combined with 2D WS 2 exfoliated layers and Ti contacts, and show record rectification ratios (>10 6 ) concurrently with ON-Current density (>10 3 A cm –2 ) for application in power rectifiers.
36 MATERIALS SCIENCE↗
Evidence for ionization damage in mid-wave infrared nBn detectors
The effects of 63 MeV proton and 60Co gamma irradiation on the operation of 4.3 μm cutoff nBn photodetectors are demonstrated separately, and both are shown to yield a total ionizing dose (TID) effect. The effect is shown here in an InAsSbBi nBn detector and has been observed in other bulk alloy nBn detectors, and is unusual as it is notably absent in superlattice nBn detectors. The non-antireflection coated detectors exhibit a pre-radiation quantum efficiency of 17% at 3.3 μm wavelength and a dark current density of 50 μA/cm2, or roughly 300× the Rule 07 expectation, at their ideal operating voltage of −0.4 V bias at 150 K. Step-wise proton irradiation and in situ measurement indicate that the dark current increases to about 400× Rule 07 at the highest proton dose level of 150 krad(Si) (9.10 × 1011 p+/cm2), while the quantum efficiency is degraded at a relatively faster rate than the majority of analogous detectors characterized by our lab. Both the photocurrent and dark current are also shown to exhibit a turn-on voltage magnitude reduction of 100 mV following either gamma or proton irradiation, a trend which is attributable to negative trapped charge at the barrier interface (TID effect). This theory is further supported by an observed capacitance density magnitude reduction with dose and affirmed with Silvaco TCAD simulations. Following both proton exposure and subsequent anneal and gamma exposure and subsequent anneal; dark current, photocurrent, and CV all approach their pre-radiation baseline values.
Physics↗
Gain characterization of LGAD sensors with beta particles and 28-MeV protons
Low Gain Avalanche Diodes, also known as LGADs, are widely considered for fast-timing applications in high energy physics, nuclear physics, space science, medical imaging, and precision measurements of rare processes. Such devices are silicon-based and feature an intrinsic gain due to a p + -doped layer that allows the production of a controlled avalanche of carriers, with multiplication on the order of 10–100. This technology can provide time resolution on the order of 20–30 ps, and variants of this technology can provide precision tracking too. The characterization of LGAD performance has so far primarily been focused on the interaction of minimum ionizing particles for high energy and nuclear physics applications. This article expands the study of LGAD performance to highly-ionizing particles, such as 28-MeV protons, which are relevant for several future scientific applications, e.g. in biology and medical physics, among others. These studies were performed with a beam of 28-MeV protons from a tandem Van de Graaff accelerator at Brookhaven National Laboratory and beta particles from a ^90Sr source; these were used to characterize the response and the gain of an LGAD as a function of bias voltage and collected charge. Here, the experimental results are also compared to TCAD simulations.
47 OTHER INSTRUMENTATION↗
Ultra-Fast 4H-SiC LGAD With Etched Termination and Field Plate
The design, fabrication, and demonstration of a novel Silicon Carbide Low Gain Avalanche Detector (4HSiC LGAD), exhibiting an ultra-fast time response and excellent time resolution, are reported. Here, the use of field plates is proposed to suppress the high electric field caused by the negative bevel-etched angle in 4H-SiC LGADs based on TCAD simulations. Experimental measurements confirm that the field plate significantly increases the breakdown voltage of the 4H-SiC LGADs. Gain and time resolution are measured by using the ultraviolet transient current technique (UV-TCT) showing that 4H-SiC LGADs possess excellent timing performance, with a time resolution better than 35 ps for the injected laser signal with single minimum ionizing particle (MIP) charges generation at room temperature. Additionally, the gain suppression effect in a 4H-SiC LGAD is observed for the first time.
43 PARTICLE ACCELERATORS↗
Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory
In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.
42 ENGINEERING↗
Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design
Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .
42 ENGINEERING↗
Electric Drive Technologies Consortium (EDTC)/ Cost competitive, high-Performance, highly Reliable (CPR) Power Devices on 4H-SiC (Final Report)
4H-Silicon carbide (4H-SiC) is a wide bandgap semiconductor that offers superior material properties over silicon, including higher critical electric field, thermal conductivity, and electron saturation velocity. These advantages make 4H-SiC highly attractive for high-voltage, high-efficiency power electronics. However, realizing the full potential of SiC requires device technologies that are not only high-performing but also manufacturable and reliable under real-world operating conditions. This report summarizes the outcomes of a five-year R&D effort funded by the U.S. Department of Energy (DOE) under the Electric Drive Technologies Consortium (EDTC), focused on developing cost-competitive, high-performance, and highly reliable (CPR) power devices on 4H-SiC substrates. The program targeted scalable and manufacturable 1.2 kV-class SiC MOSFETs optimized for next-generation electric vehicles, renewable energy systems, and industrial power conversion. The project delivered transformative advancements in SiC power device performance and ruggedness. Particularly, Specific on-resistance (R on,sp ) was reduced by up to 37%, from ~4.0 m$\Omega \cdot$cm 2 in earlier designs to an industry-leading 2.40 m$\Omega \cdot$cm 2 , driven by optimized doping, refined JFET widths, and layout engineering. Breakdown voltages (BV) exceeded 1600 V, marking improvement over legacy baselines, and demonstrating the robustness of newly implemented junction profiles and edge terminations. Short-circuit withstand time (SCWT) saw a remarkable 4$\times$ increase, from ~2 $\mu$s to over 8 $\mu$s, achieved through the successful deployment of deep P-well structures (~1.8–2.0 $\mu$m) via channeling implantation. This innovative process breakthrough enabled precise junction formation without MeV-class implantation tools, reduced leakage under high field stress, and allowed even the shortest-channel devices (down to 0.3 $\mu$m) to achieve both high BV and excellent ruggedness—breaking the traditional trade-off between conduction efficiency and blocking capability. Several novel architectures pushed the performance envelope further. JBSFETs—featuring embedded Schottky portions—eliminated bipolar degradation and drastically reduced third-quadrant leakage, while Ladder MOSFETs introduced a clever orthogonal conduction path that achieved a 15.4% reduction in R on,sp over standard linear designs. Switching performance reached new benchmarks: short-channel devices showed a 31% reduction in total switching energy compared to 0.5 $\mu$m counterparts, while maintaining manageable gate drive requirements. Layout-optimized structures not only improved transconductance but also accelerated switching transitions, pointing to real-world benefits in converter-level efficiency. The devices also passed rigorous reliability validation. Stress-tested across TDDB, HTGB, HTRB, HVP, and burn-in, the devices screened under 30 V/10 hr and 43 V/1 s protocols consistently exhibited tighter lifetime distributions and long-term oxide robustness. These screening techniques proved effective in identifying latent defects and ensuring deployment-grade reliability. Meanwhile, advanced 3D TCAD simulations revealed and resolved electric field hotspots—particularly in HEXFET corners—where fields exceeding 4.8 MV/cm were mitigated through geometry-aware layout corrections. Overall, the results of this project demonstrate a manufacturable and scalable SiC power device platform that addresses key DOE performance targets for efficient, robust, and reliable 1.2kV 4H-SiC Power Devices. The developed technologies represent a meaningful step forward in the commercial readiness of high-voltage SiC solutions and provide a strong foundation for continued advancement in wide bandgap power electronics.
42 ENGINEERING↗
Gallium Arsenide Semiconductor Opening Switches: Enabling Nanosecond High Powering Pulsed Systems
The goal of this work awas to investigate design manufacturing semiconductor opening switches (SOS) in both silicon and gallium arsenide (GaAs). Solid-state opening switches are critical components for pulsed power systems and applications in directed energy, dielectric wall accelerators, and novel semiconductor manufacturing techniques. Under this funding, we have developed silicon SOS designs that suppresses an unwanted prepulse, increases the peak output voltage by about 10 percent, and reduces the pulse rise time by ~ 4x compared with more conventional profiles. Through this effort we have improved device fabrication and bonding techniques. Additionally, work on this the GaAs opening switch has defined a unique application space that these devices are suited for. GaAs opening switches have short risetimes and pulse widths compared to silicon devices, however the short carrier lifetime of GaAs makes the circuit design more challenging than in silicon. For high PRF operation, the lifetime of the GaAs is an advantage compared to silicon. TCAD simulations of GaAs devices have been used to optimize a GaAs profile. Additionally, we have designed pulsers with sub 50ns reserve pump times and tested GaAs COTs PIN diodes in them.
42 ENGINEERING↗
High-Speed Single-Event Current Transient Measurements in SiGe HBTs
Time-resolved ion beam induced charge reveals heavy ion response of IBM 5AM SiGe HBT: 1) Position correlation. 2) Unique response for different bias schemes. 3) Similarities to TPA pulsed-laser data. Heavy ion broad-beam transients provide more realistic device response: 1) Feedback using microbeam data 2) Overcome existing issues of LET and ion range with microbeam Both micro- and broad-beam data sets yield valuable input for TCAD simulations. Uncover detailed mechanisms for SiGe HBTs and other devices fabricated on lightly-doped substrates.
Pellish, Jonathan A.↗
Heavy Ion Current Transients in SiGe HBTs
Time-resolved ion beam induced charge reveals heavy ion response of IBM 5AM SiGe HBT: a) Position correlation[ b) Unique response for different bias schemes; c) Similarities to TPA pulsed-laser data. Heavy ion broad-beam transients provide more realistic device response: a) Feedback using microbeam data; b) Overcome issues of LET and ion range with microbeam. Both micro- and broad-beam data sets yield valuable input for TCAD simulations. Uncover detailed mechanisms for SiGe HBTs and other devices fabricated on lightly-doped substrates.
Pellish, Jonathan A.↗
Heavy-Ion-Induced Degradation in SiC Schottky Diodes: Incident Angle and Energy Deposition Dependence
Heavy-ion-induced degradation in the reverse leakage current of SiC Schottky power diodes exhibits a strong dependence on the ion angle of incidence. This effect is studied experimentally for several different bias voltages applied during heavy-ion exposure. In addition, TCAD simulations are used to give insight on the physical mechanisms involved.
Javanainen, Arto↗
Heavy Ion Induced Degradation in SiC Schottky Diodes: Bias and Energy Deposition Dependence
Experimental results on ion-induced leakage current increase in 4H-SiC Schottky power diodes are presented. Monte Carlo and TCAD simulations show that degradation is due to the synergy between applied bias and ion energy deposition. This degradation is possibly related to thermal spot annealing at the metal semiconductor interface. This thermal annealing leads to an inhomogeneity of the Schottky barrier that could be responsible for the increase leakage current as a function of fluence.
modeling↗