FOSS CAD for the Compact Verilog-A Model Standardization in Open Access PDKs
This is a conference paper about open source tools for circuit simulation and model compilers.
Grabinski, Wladek↗
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ghostbus v0.1.0
Ghostbus is a Verilog meta-scripting tool which automates memory map creation, address assignment, and bus routing much like Register Description Language (RDL) and SystemRDL, but with a few stark differences. First, the design is entirely defined/captured within the Verilog/SystemVerilog codebase (no extra second language). Second, the Verilog code remains valid even without the auto-generated code, enhancing modularity and compatibility with other tools/workflows.
Huang, Gang [Lawrence Berkeley National Laboratory↗
Graph-based Compact Modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach
Parameter extraction of compact transistor models is an expensive process, heavily relying on engineering knowledge and experience. To automate such a process, we propose a novel approach, Graph-based Compact Model (GCM), that integrates physical modeling and data-driven learning. GCM utilizes Graph Neural Networks (GNNs) to establish the model structure, while retaining the physicality in compact models. Here, we implement our GCM in Verilog-A to support circuit simulations. As demonstrated with an academic 7 nm FinFET PDK, the new approach automatically generates a GCM model within a minute, and achieves excellent accuracy and efficiency in SPICE.
42 ENGINEERING↗
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Analog-to-digital converter↗
Invited: Software defined accelerators from learning tools environment
Next generation systems, such as edge devices, will need to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. In this paper we present the Software Defined Accelerators From Learning Tools Environment (SODALITE), an automated open source high-level ML framework-to-verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets. The SODALITE approach will implement optimal designs by seamlessly combining custom components generated through high-level synthesis (HLS) with templated and fully tunable Intellectural Properties (IPs) and macros, integrated in an extendable resource library. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimensions.
High-Level Synthesis, Accelerators, Hardware-Softw↗
Compiler-Driven FPGA Virtualization with SYNERGY
FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in datacenters. Applications in datacenters run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software atsub-clock-tickgranularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is availabletoday.We use Synergy to virtualize FPGA workloads across a cluster of Intel SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3--4x of unvirtualized performance, and incur a modest increase in FPGA fabric usage.
Computer Science↗
P38 heterogeneous multi-tiled system with support for message queues (MoSAIC) v0.1
The proposed system is written in the hardware description language (HDL) verilog targeting an FPGA board. It is intended as a testbed to explore architecture tradeoffs in multi-tiled heterogeneous architectures. Although we target FPGAs, the system can be implemented as a monolithic SoC or a package comprised of many chiplets that are interconnected in the same package using a NoC. The proposed NoC is lightweight and follows an axi-lite interface. The endpoints of the NoC are a heterogeneous mix of "tiles" as endpoints that are general purpose processors, fixed function accelerators, and programmable accelerators. We assume that the network interfaces for the NoC endpoints are all addressable in a global name-space in that they represent an address range (for memory addresses) or a range of unique identifiers that are associated with each individual tile. This makes the functionality abstract from the standpoint of the NoC design details. Message queues offer a direct inter-processor interface between peer general purpose cores and diverse accelerators that comprise an SoC. Although they share the same NoC infrastructure for inter-tile communication within an SoC or SiP, the hardware message queues bypass the memory hierarchy and thus do not pollute the memory state or invoke the cache coherence mechanism.
Gonzalez, LouisaPatricia↗
pnnl/OpenCGRA
OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs. The first open-source integrated framework able to support the full top-to-bottom design flow for specializing and implementing CGRAs: modeling at different abstraction levels (functional level, cycle level, register-transfer level) with compiler support, verification at different granularities (unit testing, integration testing, property-based testing), simulation, generation of synthesizable Verilog, and characterization (area, power, and timing).
Cheng, Tan↗
Generic Multi-Layer Perceptron Inference Accelerator on FPGA (vneuron) v1.0
We have designed and implemented a neural network inference compute engine (vneuron) that can be deployed in the fabric of any FPGA without using special hardware accelerator primitive. The "vneuron" is purely written in verilog, and supports scalable neural network structure with fully connected layers and ReLU activation ( Multi-Layer Perceptron architecture) with 16 bits of precision. We have demonstrated it on an Xilinx Artix 7 FPGA for a 16-input, 8-output MLP with 3 layer, 1600 parameters. It takes 40 DSP48E and 40 BRAM18, and takes 131 clock cycles for computing (1048 ns when clocked at 125MHz). We include PyTorch quantization from a given floating point model, and provide behavioral verification simulation in the disclosed software package.
Du, Qiang↗
ESnet SmartNIC v1.0
The ESnet SmartNIC is a collection of Verilog based FPGA design software, as well as drivers to interact with the FPGA. It provides an infrastructure framework for FPGA based hardware acceleration of network packet use cases. Different research and production applications can be easily written for the SmartNIC. Its advantage is that it reduces the development time for new applications by providing a pre-existing shell library for common functions.
Mah, Bruce↗
Hyperdimensional computing for image classification (HDC) v1.0
This is an implementation of the hyperdimensional computing technique to classify images. It consists of a python script that trains the system for a set of images from a set of images (dataset) specified by the user. This training produces hardware configuration parameters and description vectors that are then loaded into the hardware description part of the project. The hardware description consists of hardware described in Verilog (a well known language for this purpose) that is synthesizable and can be implemented in a real chip. This hardware received the training information generated by python, and then is able to accept images to produce answers for each image on which category (class) from the pre-=trained ones the image belongs to. The hardware and python training scripts are configurable and documented. The advantage of hyperdimensional computing is its robustness to errors and the easy capability for online learning (refining the training during inference slowly over time), which this implementation supports.
Michelogiannakis, Georgios [Lawrence Berkeley Nati↗
Digital Application Specific Integrated Circuit Design
Single radiation effects can be transient and static. The charge collected from radiation has a prompt (drift) and a slow (diffusion) component. This current spike causes disparate results: SEU, SET, SEB, MBU, and more. A system level SEE mitigation technique, used to overcome, is the triple module redundancy (TMR). TMR for system Verilog (TMR4SV), written in Python, is the first step towards design IP triplication. It allows various triplication methods for flip flops, clocks, and logic.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Application Note: Mixed Signal Simulation with Xyce™ 7.1
This application note describes how Release 7.1 of the Xyce circuit simulator can be coupled with external simulators via either a Python-based interface that leverages the Python ctypes foreign function library or via the Verilog Procedural Interface (VPI). It also documents the usage of these interfaces on RHEL7 with Python 2.6 or 2.7. These interfaces are still under development and may change in the future. So, a key purpose of this application note is to solicit feedback on these interfaces from both internal Sandia Xyce users and other performers on the DARPA Posh Open Source Hardware (POSH) program.
97 MATHEMATICS AND COMPUTING↗
Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications
Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.
22 GENERAL STUDIES OF NUCLEAR REACTORS↗
GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics
Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.
22 GENERAL STUDIES OF NUCLEAR REACTORS↗
Practical Probabilistic Programming
Recent advances in probabilistic programming languages (PPLs) have provided the capability for exact inference: computing a closed-form probability distribution for a given probabilistic program. In particular, the new language Roulette uses a language oriented programming (LOP) approach, wherein analysts build new programming languages on top of a set of primitives provided by Roulette, which then translates these structures into a weighted model counting problem which can be solved by automated reasoning tools. However, because Roulette provides few convenience features, developing these new languages is challenging even for expert users. We developed a standard library of common probability functions for Roulette with the goal of improved usability. This included approximation of continuous probability density functions using discrete probability mass functions. We demonstrated this approach by modeling a cosmic ray striking a RAM controller. We found that Roulette provides a powerful interface for highly expressive probabilistic programs to be generated. In collaboration with the NNSA Advanced Simulation and Computing program, which resulted in development of a tool called Circulette, we were able to model complex circuits expressed in Verilog using probabilistic programs with an expressivity not previously possible. Our research question that motivated the development of a Roulette standard library was to determine whether non-experts could use a PPL to model relevant problems regarding radiation effects on microelectronics. This standard library improved the expressivity of Roulette by implementing common probability density functions, mathematical operators on distributions, and support for empirical distributions. While Roulette is a powerful modeling language, the untyped, LOP approach makes error messages difficult to understand and requires expert aid. We recommend further research on Roulette, especially with its error messages, to enable improved usability. At the same time, this project demonstrated that for users familiar with Roulette and the LOP approach, Roulette provides powerful new capabilities that can be integrated with other Sandia modeling capabilities.
97 MATHEMATICS AND COMPUTING↗
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators
Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension
Minutoli, Marco↗
A Memory Efficient Lock-Free Circular Queue
Hardware queues are import in many applications, such as data transfer, synchronization of concurrent modules with the need of mutual exclusion constructs. State of the art bounded (of a fixed size) lock free circular queues are implemented either by read/write atomic operations, or barrier conditions, or by separating dequeue and enqueue operations. However, these queues always require an unused element at all the times to safe-guard the front and rear pointers of the queue, so as to avoid data race conditions, which leads to the waste of memory. The waste of memory is especially disadvantageous in applications such as I/O data transfer, and image transfer between processing filters, when large element size is needed, We propose a lock-free solution of the bounded circular queue through read/write atomic operations, but without the need of an extra element in the queue. The proposed solution is implemented and verified in both Verilog and ’C’ languages. We also demonstrate its effectiveness by comparing its area and delay metrics with the implementations of other existing designs of queue.
Miniskar, Narasinga Rao↗