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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Thermoradiative Conversion for Space Power Systems

The thermoradiative cell is a new method for converting heat energy to electrical power, first detailed by Strandberg in 2015. The cell is structurally similar to a photovoltaic cell, in that it is a p-n junction semiconductor device, but thermodynamically operates in the reverse direction, converting the thermal dark current into electrical power by utilizing the recombination radiation from thermally-generated electron hole pairs to radiate waste heat to space. This technology may have application for space missions in converting thermal energy produced by a radioisotope source or from a nuclear reactor into power. The power and efficiency can be calculated as a function of bandgap in the detailed-balance case (the Shockley-Queisser limit), in which all of the thermal emissivity of the cell is due to the recombination of thermally generated electron-hole pairs, and all other recombination losses are ignored. The current produced is directly proportional to the recombination radiation, and thus the more thermally generated pairs, the higher the current. The voltage is proportional to the external bias. These two constraints allow optimization of the optimum bias point for maximum power, and allow calculation of the efficiency at maximum power point. Unlike photovoltaic cells, the maximum power operating point is not the same as the maximum efficiency point, and higher efficiency can be achieved at a higher (negative) bias in the ideal case. Incorporating non-ideal losses, however, shifts the maximum efficiency point toward lower bias. Since a thermoradiative cell operates by radiating directly to space, the current produced by a themoradiative cells will increase with the Stefan-Boltzman radiative efficiency; roughly the fourth power of the temperature. Thus, in contrast to a photovoltaic converter, the power produced is highest at high operating temperatures. Likewise, in contrast to conventional thermal conversion, high radiator temperature increases, rather than decreases the efficiency. Thus, the thermoradiative conversion may fill a mission niche in which small radiator size is required. The basic operation will be summarized, applications to space power discussed, and the requirements for further research outlined.

Photovoltaic Cell↗
DOE OSTI2025

Real-Time Lifetime Prediction of Semiconductor Devices Using Hardware-in-the-Loop

This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.

hardware-in-the-loop (HIL)↗
DOE OSTI2026

Lithography-Free Mesa Isolation by Laser Ablation for Multijunction III-V Photovoltaic Space Power Generation

Eliminating photolithography from photovoltaic device processing is a significant opportunity for cost reduction and increased manufacturing throughput. In this work, we test femtosecond laser ablation and scribing as an alternative to contact photolithography and wet chemical etching for mesa isolation of multijunction devices. We demonstrate that upright multijunction devices isolated by using the laser as a scribe to cleave through the substrate had virtually no performance loss when compared to a baseline device processed with photolithography. By contrast, devices isolated by laser ablating through the active layers have performance losses that cannot be fully eliminated with postprocess etching. This demonstration of photolithography-free mesa isolation with no performance losses is promising as a pathway to less expensive and higher throughput III-V device manufacturing.

14 SOLAR ENERGY↗
NASA NTRS1991

Silicon carbide, an emerging high temperature semiconductor

In recent years, the aerospace propulsion and space power communities have expressed a growing need for electronic devices that are capable of sustained high temperature operation. Applications for high temperature electronic devices include development instrumentation within engines, engine control, and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Other earth-based applications include deep-well drilling instrumentation, nuclear reactor instrumentation and control, and automotive sensors. To meet the needs of these applications, the High Temperature Electronics Program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. Research is focussed on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of silicon carbide electronic devices and integrated sensors. The progress made in developing silicon carbide is presented, and the challenges that lie ahead are discussed.

Matus, Lawrence G.↗
DOE OSTI2020

HPC4Mfg with Samsung: Making semiconductor devices cool through HPC ab initio simulations

For decades, the semiconductor technology has followed the Moore’s law, making newer devices more powerful and energy efficient. Recently, however, it has reached a point where the performance and the energy efficiency of the device do not improve with the shrinking device size. One of the fundamental reasons of this deviation from the past trend is the interconnect resistance, which becomes larger with the shrinking size. The devices size is so small that the quantum mechanical effects can no longer be ignored and the traditional continuum simulation tools such as TCAD become inadequate. In this project, Samsung Semiconductor Inc. and Lawrence Berkeley National Laboratory has collaborated to perform first of kind device-scale ab initio simulations to optimize materials and interconnect morphology to minimize interconnect resistance. We have tested the use of LS3DF method and the PEtot_trans approach on top of the folded spectrum method (FSM) Escan code to calculate the scattering state, and to study various effects influence the interconnect conductivity. We found that, the LS3DF can be used to calculate such metallic system. On the other hand, the use of Escan code to solve the linear equation is not practical due to the slow convergence. We have implemented a Chebyshev filter technique to calculate a few hundred eigen states near the scattering state energy E, then use these eigen states as preconditioner to solve the linear equation. We have used this approach to study the different factors which affect the interconnect conductivity, including the shape, the point defect, the temperature, and the grain boundary.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
NASA NTRS2001

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Powell, J. Anthony↗
DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗
NASA NTRS2010

Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the switch and the inductor configuration. In the fault condition, both the resistor and the inductor react immediately. The resistor reacts by allowing more current to flow and dropping the voltage. Initially, the inductor reacts by dropping the voltage, and then by not allowing the current to change. When the comparator detects the drop in voltage, it opens the switch, thus preventing any further current flow. The inductor alone is not sufficient protection, because after the voltage drop has settled, the inductor would then allow the current to change, in this example, the current would be 3.7 A. In the fault condition, the resistor is flowing 200 mA until the fuse blows (anywhere from 1 ms to 100 s), while the switch and inductor combination is flowing about 2 A test current while monitoring for the fault to be corrected. Finally, as an additional safety feature, the circuit can be configured to hold the switch opened until both the load and source are disconnected.

Burns, Bradley M.↗
NASA NTRS1996

Semiconductor Laser Low Frequency Noise Characterization

This work summarizes the efforts in identifying the fundamental noise limit in semiconductor optical sources (lasers) to determine the source of 1/F noise and it's associated behavior. In addition, the study also addresses the effects of this 1/F noise on RF phased arrays. The study showed that the 1/F noise in semiconductor lasers has an ultimate physical limit based upon similar factors to fundamental noise generated in other semiconductor and solid state devices. The study also showed that both additive and multiplicative noise can be a significant detriment to the performance of RF phased arrays especially in regard to very low sidelobe performance and ultimate beam steering accuracy. The final result is that a noise power related term must be included in a complete analysis of the noise spectrum of any semiconductor device including semiconductor lasers.

SEMICONDUCTOR LASERS↗
NASA NTRSDate not supplied

Wide Bandgap Semiconductor Devices & Systems for Communications in Extreme Environment

The feasibility of Ka-band gallium nitride (GaN) based high power amplifier (HPA) for signal amplification in extreme planetary environment is investigated and its measured performance is presented. The data includes Pout, PAE, EVM for several waveforms and data rates, output spectrum, IMD, Noise Figure, and Gain. The data indicates excellent overall performance. Potential application of this HPA includes communication systems required to operate in the extreme hot environment of Mercury and Venus, extreme cold and high radiation environment of Jupiter’s icy moons, and Artemis missions that involve human/robotic exploration and long-term presence on the Moon.

Gallium Nitride↗
DOE OSTI2024

Slope Efficiency and Voltage Reduction at High Current Densities in AlInGaAs Diode Lasers

Here, the slope efficiency and drive voltage of broad area AlInGaAs laser diodes near 865 nm is observed to decrease significantly under quasi-CW pulsed operation at currents well above threshold, in a manner that cannot be explained by thermal effects or carrier leakage over heterojunction barriers. Simulations show that the slope efficiency reduction is explicable by increased free carrier absorption in the waveguide region. Empirical formulas are presented to represent these effects in a closed analytic form suitable for use in simulators for diode-pumped laser systems.

47 OTHER INSTRUMENTATION↗
NASA NTRS1979

Transistor step stress program for JANTX2N4150

Reliability analysis of the transistor JANTX2N4150 manufactured by General Semiconductor and Transitron is reported. The discrete devices were subjected to power and temperature step stress tests and then to electrical tests after completing the power/temperature step stress point. Control sample units were maintained for verification of the electrical parametric testing. Results are presented.

Source record↗
NASA NTRS1980

JANTX1N5622 diode

Report describes effects of power and temperature overstress on Semtech and Micro Semiconductor diodes. Semtech devices failed with excessive reverse bias leakage due to external paint. Micro Semiconductor diodes had reverse bias leakage failure due to damaged silicon.

Source record↗
NASA NTRS1991

Semiconductor Laser With Multilayer Dielectric Reflector

Multilayer dielectric reflector included in proposed surface-emitting, distributed-feedback, grating semiconductor laser (e.g., a GaAlAs device). Contributes to efficiency and output power of laser by reducing amount of light entering substrate, where wasted by absorption. Index of refraction in reflector sublayers alternates between higher and lower value. Higher value less than effective index of refraction of waveguide layer.

Lang, Robert J.↗
DOE OSTI2024

High-voltage AlN Schottky barrier diodes on bulk AlN substrates by MOCVD

Abstract This letter reports the demonstration of Aluminum nitride (AIN) Schottky barrier diodes on bulk AlN substrates by metalorganic chemical vapor phase deposition with breakdown voltages exceeding 3 kV. The devices exhibited good rectifying characteristics with ON/OFF ratios of 10 6 –10 8 and excellent thermal stability from 298 to 623 K. The device Schottky barrier height increased from 0.89 to 1.85 eV, and the ideality factor decreased from 4.29 to 1.95 with increasing temperature, ascribed to the inhomogeneous metal/AlN interface. This work demonstrates the potential of AlN as an ultra-wide bandgap semiconductor for developing multi-kV AlN high-voltage and high-power devices.

Physics↗
DOE OSTI2022

Electronic and optical characterization of bulk single crystals of cubic boron nitride (cBN)

Cubic boron nitride (cBN) is a relatively less studied wide bandgap semiconductor despite its many promising mechanical, thermal, and electronic properties. We report on the electronic, structural, and optical characterization of commercial cBN crystal platelets. Temperature dependent transport measurements revealed the charge limited diode behavior of the cBN crystals. The equilibrium Fermi level was determined to be 0.47 eV below the conduction band, and the electron conduction was identified as n-type. Unirradiated dark and amber colored cBN crystals displayed broad photoluminescence emission peaks centered around different wavelengths. RC series zero phonon line defect emission peaks were observed at room temperature from the electron beam irradiated and oxygen ion implanted cBN crystals, making this material a promising candidate for high power microwave devices, next generation power electronics, and future quantum sensing applications.

36 MATERIALS SCIENCE↗