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At least 217 records · Page 12

Radiation damage in MOS integrated circuits, Part 1

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Danchenko, V.↗

P-channel silicone gate FET

Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.

Ostis, S.↗

A linear voltage-tunable distributed null device.

A linear voltage-tunable null device was predicted, fabricated, and tested. This filter is conceptually a distributed parameter RC representation of the channel of a MOSFET in a network configuration with a second MOSFET that is treated as a variable resistor. Classical transmission-line theory is used to predict a linear tuning curve with applied bias for the device. This concept was used to design a null device having a null that is linearly tunable in the range of 100 kHz. Such devices were fabricated and tested. Typical MOS processing steps were used and the resulting structures are compatible with the planar technology. The compatibility leads towards extension of this work to different frequency ranges for other specific applications.

Benz, H. F.↗

A study of trends and techniques for space base electronics

The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.

Trotter, J. D.↗

Trends and Techniques for Space Base Electronics

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.

Trotter, J. D.↗

High-voltage, high-power, solid-state remote power controllers for aerospace applications

Two general types of remote power controller (RPC) that combine the functions of a circuit breaker and a switch were developed for use in direct-current (dc) aerospace systems. Power-switching devices used in these designs are the relatively new gate-turnoff thyristor (GTO) and poweer metal-oxide-semiconductor field-effect transistors (MOSFET). The various RPC's can switch dc voltages to 1200 V and currents to 100 A. Seven different units were constructed and subjected to comprehensive laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times to limit voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout and microsecond tripout for large overloads. The basic circuits developed can be used to build switchgear limited only by the ratings of the switching device used.

Sturman, J. C.↗

Electrical performance of semiconductor devices at cryogenic temperatures

The electrical performance of semiconductor devices is examined over the temperature range from 300 to 1.4K The design, fabrication, and testing of p-channel field effective transistors (MOSFET) are emphasized to develop a device that will perform satisfactorily in the temperature range from 4.2 to 1.4K. The current-voltage characteristics of the device are obtained as a function of temperature for varying channel lengths and channel dopant levels. The MOSFET's with average channel lengths of 3.27, 5.68, 8.37, and 11.39 microns are examined. It is indicated that the devices with the shorter channel lengths perform better in the 4 to 20K range than those with the longer channel lengths.

Ventrice, C. A.↗

Advanced detectors and signal processing for bubble memories

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Results of bubble film annealing indicate that a low temperature silicon on garnet technology is the most likely one to succeed commercially. Annealing ambients are also shown to have a major effect on the magnetic properties of bubble films. Functional MOSFETs were fabricated on bubble films coated with thick (approximately 1 micron) SiO2 layers. The two main problems with these silicon on garnet MOSFETs are low electron mobilities and large gate leakage currents. Results indicate that the laser recrystallized silicon and gate oxide (SiO2) layers are contaminated. The data suggest that part of the contaminating ions originate in the sputtered oxide spacer layer and part originates in the bubble film itself. A diffusion barrier, such as silicon nitride, placed between the bubble film and the silicon layer should eliminate the contamination induced problem.

Kryder, M. H.↗

Monolithic lead salt-silicon focal plane development

This paper is a summary of work done in the development of monolithic lead salt-silicon infrared focal plane technology. The photoconductive detector materials, PbS and PbSe are chemically deposited onto premetallized silicon MOSFET integrated circuit wafers. A variety of structures based on an implanted PMOS process were fabricated and evaluated. Operational results of an eight-element PbS array multiplexed on-chip are presented along with radiometric measurements on other integrated PbS-silicon MOSFET structures. PbS imagery is shown using one element of a 20-element array integrated on-chip.

Barrett, J. R.↗

The feasibility of silicon on garnet technology

The feasibility of combining silicon and magnetic bubble technologies is demonstrated. Functional MOSFETs have been fabricated on top of bubble films coated with 1-micron thick SiO2 layers. The large grain silicon necessary for these devices is obtained by laser recrystallization of polycrystalline silicon (polysilicon). The laser-recrystallization process causes changes in the magnetic properties of the bubble film; however, these changes can be reversed by subsequent thermal anneals. The required temperature treatments after laser annealing are compatible with the MOSFET fabrication process.

Rasky, P. H. L.↗

Design of high-voltage, high-power, solid state remote power controllers for aerospace applications

Two general types of remote power controllers (RPC's), which combine the functions of a circuit breaker and a switch, were developed for use in dc aerospace systems. Power-switching devices used in the designs are the gate-turnoff thyristor (GTO) and MOSFET. The RPC's can switch dc voltages to 1200 V and currents to 1000 A. Seven different units were constructed and subjected to laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times which limit surge currents and voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout proportional to I sq T and microsecond tripout for large overloads.

Sturman, J. C.↗

Overcash, D. R.

The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.

Source record↗

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Jones, C. W.↗

Parameter extraction and transistor models

Using specified mathematical models of the MOSFET device, the optimal values of the model-dependent parameters were extracted from data provided by the Jet Propulsion Laboratory (JPL). Three MOSFET models, all one-dimensional were used. One of the models took into account diffusion (as well as convection) currents. The sensitivity of the models was assessed for variations of the parameters from their optimal values. Lines of future inquiry are suggested on the basis of the behavior of the devices, of the limitations of the proposed models, and of the complexity of the required numerical investigations.

Rykken, Charles↗

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗

Development of a unit cell for a Ge:Ga detector array

Two modules of gallium-doped germanium (Ge:Ga) infrared detectors with integrated multiplexing readouts and supporting drive electronics were designed and tested. This development investigated the feasibility of producing two-dimensional Ge:Ga arrays by stacking linear modules in a housing capable of providing uniaxial stress for enhanced long-wavelength response. Each module includes 8 detectors (1x1x2 mm) mounted to a sapphire board. The element spacing is 12 microns. The back faces of the detector elements are beveled with an 18 deg angle, which was proved to significantly enhance optical absorption. Each module includes a different silicon metal-oxide semiconductor field effect transistor (MOSFET) readout. The first circuit was built from discrete MOSFET components; the second incorporated devices taken from low-temperature integrated circuit multiplexers. The latter circuit exhibited much lower stray capacitance and improved stability. Using these switched-FET circuits, it was demonstrated that burst readout, with multiplexer active only during the readout period, could successfully be implemented at approximately 3.5 K.

Source record↗

Propagation delay measurements from a timing sampler intended for use in space

A 3-micron CMOS timing sampler is described which is a test circuit designed into the Jet Propulsion Labs' CRRES chip to be flown on the Combined Release and Radiation Effects Satellite (CRRES). The timing sampler consists of 64 inverter-pair stages with sampling latches and decoder circuitry. The sampler is used to measure inverter-pair propagation delays, which are nominally 2.5 ns, with a resolution of 100 ps. A simple model was developed to explain the radiation-induced inverter-pair delay shifts in terms of radiation-induced MOSFET threshold-voltage shifts and effective modal capacitances. The magnitude of the shift in pair delay with radiation was estimated at the point where the n-MOSFET threshold voltage became zero. For a 0.7-V-threshold shift, the pair delay increased from its preradiation value by 360 ps for a rising step input and decreased by 190 ps for a falling step input.

Blaes, B. R.↗

Models of second-order effects in metal-oxide-semiconductor field-effect transistors for computer applications

Second-order effects in metal-oxide-semiconductor field-effect transistors (MOSFETs) are important for devices with dimensions of 2 microns or less. The short and narrow channel effects and drain-induced barrier lowering primarily affect threshold voltage, but formulas for drain current must also take these effects into account. In addition, the drain current is sensitive to channel length modulation due to pinch-off or velocity saturation and is diminished by electron mobility degradation due to normal and lateral electric fields in the channel. A model of a MOSFET including these considerations and emphasizing charge conservation is discussed.

Benumof, Reuben↗