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At least 37 records · Page 2

Lithium Circuit Test Section Design and Fabrication

The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper will discuss the overall system design and build and the component testing findings.

Godfroy, Thomas↗

Modifications and Modeling of the Fission Surface Power Primary Test Circuit (FSP-PTC)

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Performance of the ALIP, provided by Idaho National Laboratory (INL), will be evaluated when testing resumes. Data from the first round of testing has been used to refine the working system model, developed using the Generalized Fluid System Simulation Program (GFSSP). This paper covers the modifications of the FSP-PTC and the updated GFSSP system model.

Garber, Anne E.↗

Modifications and Modelling of the Fission Surface Power Primary Test Circuit (FSP-PTC)

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of the Single Flow Cell Test Apparatus (SFCTA) in the test section. Performance of the ALIP, provided by Idaho National Laboratory (INL), will be evaluated when testing resumes. The SFCTA, which will be tested simultaneously, will provide data on alkali metal flow behavior through the simulated core channels and assist in the development of a second generation thermal simulator. Additionally, data from the first round of testing has been used to refine the working system model, developed using the Generalized Fluid System Simulation Program (GFSSP). This paper covers the modifications of the FSP-PTC and the updated GFSSP system model.

Garber, Ann E.↗

Recent Updates to the Fission Surface Power Primary Test Circuit (FSP-PTC)

An actively pumped alkali metal flow circuit, designed and fabricated at the NASA Marshall Space Flight Center, underwent a range of tests at MSFC in early 2007. During this period, system transient responses and the performance of the liquid metal pump were evaluated. In May of 2007, the circuit was drained and cleaned to prepare for multiple modifications: the addition of larger upper and lower reservoirs, the installation of an annular linear induction pump (ALIP), and the inclusion of a closeable orifice in the test section. Modifications are now complete and testing has resumed. Performance of the ALIP, provided by Idaho National Laboratory (1NL), is the subject of the first round of experimentation. This presentation details the physical changes made to the FSP-PTC and the current test program.

Garber, Anne E.↗

Addressable-Matrix Integrated-Circuit Test Structure

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

Sayah, Hoshyar R.↗

Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits

A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-micron n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 micron was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV sq cm/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV sq cm/mg was determined.

Blaes, B. R.↗

Chain Of Test Contacts For Integrated Circuits

Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.

Lieneweg, Udo↗

Testing Fixture For Microwave Integrated Circuits

Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

Romanofsky, Robert↗

Development of automated test procedures and techniques for LSI circuits

Testing of large scale integrated (LSI) logic circuits was considered from the point of view of automatic test pattern generation. A system for automatic test pattern generation is described. A test generation algorithm is presented that can be applied to both combinational and sequential logic circuits. Also included is a programmed implementation of the algorithm and sample results from the program.

Carroll, B. D.↗

Test results for SEU and SEL immune memory circuits

Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.

Wiseman, D.↗

Nearly Direct Measurement of Relative Permittivity

A recently conceived technique for determining the relative permittivity of a material sample at a given frequency is more nearly direct than are prior techniques that involve measurement of such related non-electrical quantities as the size, shape, and/or weight of the specimen. The present technique involves only measurement of two voltages at the frequency in question, followed by calculation of the ratio between the voltages. The technique requires two circuits a test circuit and a reference circuit that are identical except as described below. Each circuit includes a capacitor C1 connected in series with a much larger capacitor C2 to form a voltage divider (see figure). C1 is a parallel-plate capacitor. The top electrode of C1 is connected to an AC signal source of voltage Va at the frequency of interest. The top electrode of C1 is surrounded by a guard electrode that, in turn, is surrounded by a grounded electrode. The bottom electrode of C1 is connected to the top electrode of C2. The bottom electrode of C2 is grounded. The volume enclosed by the top, bottom, and guard electrodes of C1 constitutes a sample cell. A material sample, having relative permittivity k at the frequency of interest, is placed in the sample cell. The exact shape and size of the sample volume is not critical and can be chosen to fit the material sample. What is critical is that (a) C2 in both circuits be identical and (b) the sample cell in the test circuit have the same size and shape as that in the reference circuit, so that the capacitances of the two sample cells are proportional to the permittivities of their contents.

Calle, Carlos I.↗

Testing integrated circuits by photoexcitation

System for testing integrated circuits uses photoexcitation to determine quality of internal elements inaccessible to electrical tests. Approach prevents direct monitoring of internal operation of circuit by measurements at external terminals and is superior to electron beam scanning due to nondestructiveness.

Erickson, J. J.↗