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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

Single event upset (SEU) of semiconductor devices - A summary of JPL test data

The data summarized describe single event upset (bit-flips) for 60 device types having data storage elements. The data are from 15 acceleration tests with both protons and heavier ions. Tables are included summarizing the upset threshold data and listing the devices tested for heavy ion induced bit-flip and the devices tested with protons. With regard to the proton data, it is noted that the data are often limited to one proton energy, since the tests were usually motivated by the engineering requirement of comparing similar candidate devices for a system. It is noted that many of the devices exhibited no upset for the given test conditions (the maximum fluence and the maximum proton energy Ep are given for these cases). It is believed, however, that some possibility of upset usually exists because there is a slight chance that the recoil atom may receive up to 10 to 20 MeV of recoil energy (with more energy at higher Ep).

Nichols, D. K.↗
NASA NTRS1990

General upper bound on single-event upset rate

A technique of predicting an upper bound on the rate at which single-event upsets due to ionizing radiation occur in semiconducting memory cells is described. The upper bound on the upset rate, which depends on the high-energy particle environment in earth orbit and accelerator cross-section data, is given by the product of an upper-bound linear energy-transfer spectrum and the mean cross section of the memory cell. Plots of the spectrum are given for low-inclination and polar orbits. An alternative expression for the exact upset rate is also presented. Both methods rely only on experimentally obtained cross-section data and are valid for sensitive bit regions having arbitrary shape.

Chlouber, Dean↗
NASA NTRS1995

Single Event Upset Effects on the Clementine Solid State Data Recorder

The sensitivity of the Clementine 2.1 Gbit Solid State Data Recorder (SSDR) to single event upsets was characterized in ground tests. Subsequent in-situ measurements of the ambient radiation environment by experiments on-board Clementine permitted evaluation of the ability of models of the single event phenomenon in the SSDR to be tested using actual data. Initial results from the analysis reveal a nearly constant background upset rate of ~71 bit flips/day for the SSDR. There is no obvious correlation with a solar proton event recorded by Clementine and several other spacecraft on 20-21 February 1994, indicating that the SSDR was not sensitive to protons. The constant rate is thus interpreted as being a function of the Galactic Cosmic Ray heavy ion environment. A pronounced lunar orbit altitude dependence has also been identified in the data though the cause has not yet been unambiguously identified.

Clementine↗
NASA NTRS1983

Modeling of single-event upset in bipolar integrated circuits

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Zoutendyk, J. A.↗
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS1988

Studies Of Single-Event-Upset Models

Report presents latest in series of investigations of "soft" bit errors known as single-event upsets (SEU). In this investigation, SEU response of low-power, Schottky-diode-clamped, transistor/transistor-logic (TTL) static random-access memory (RAM) observed during irradiation by Br and O ions in ranges of 100 to 240 and 20 to 100 MeV, respectively. Experimental data complete verification of computer model used to simulate SEU in this circuit.

Zoutendyk, J. A.↗
NASA NTRS2017

Heavy Ion and Proton-Induced Single Event Upset Characteristics of a 3D NAND Flash Memory

We evaluated the effects of heavy ion and proton irradiation for a 3D NAND flash. The 3D NAND showed similar single-event upset (SEU) sensitivity to a planar NAND of identical density in the multiple-cell level (MLC) storage mode. The 3D NAND showed significantly reduced SEU susceptibility in single-level-cell (SLC) storage mode. Additionally, the 3D NAND showed less multiple-bit upset susceptibility than the planar NAND, with fewer number of upset bits per byte and smaller cross sections overall. However, the 3D architecture exhibited angular sensitivities for both base and face angles, reflecting the anisotropic nature of the SEU vulnerability in space. Furthermore, the SEU cross section decreased with increasing fluence for both the 3D NAND and the Micron 16 nm planar NAND, which suggests that typical heavy ion test fluences will underestimate the upset rate during a space mission. These unique characteristics introduce complexity to traditional ground irradiation test procedures.

3D NAND Flash memory; radiation susceptibility; si↗
NASA NTRS2002

Single event upset susceptibility testing of the Xilinx Virtex II FPGA

Heavy ion testing of the Xilinx Virtex IZ was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA is used to reveal L1/e values and single-event-functional interrupt failures.

FPGA Xilinx Virtex static test single event upset↗
NASA NTRS2017

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Field Programmable Gate Array (FPGA); Triple Modul↗
NASA NTRS1986

Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS2006

Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

The RADSAFE simulation framework is described and applied to model Single Event Upsets (SEU) in a 0.25 micron CMOS 4Mbit Static Random Access Memory (SRAM). For this circuit, the RADSAFE approach produces trends similar to those expected from classical models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

Warren, Kevin M.↗
NASA NTRS1985

Trends in parts susceptibility to single event upset from heavy ions

New test data have been combined with published data to form a nearly comprehensive body of single event upset (SEU) test data for heavy ion irradiations. These data have been arranged to exibit the SEU susceptibility of devices by function, technology, and manufacturer. Clear trends emerge which should be useful in predicting future device performance.

Nichols, D. K.↗
NASA NTRS1982

The dependence of single event upset on proton energy /15-590 MeV/

Low earth orbit satellite and Jupiter orbiter probe semiconductor devices may incur soft errors or single event upsets, manifested as bit flips, during exposure to such nuclear particles or heavy ions as trapped protons with energies ranging up to 1000 MeV. Experimental data is given on the average proton fluence needed to cause a bit flip as a function of proton energy for isoplanar bipolar TTL RAMs. Error dependence data shape and threshold energy can be related to the existing body of theoretical data on energy deposition following proton nuclear reactions. Experimental data also show that the relative cross sectional amplitude for functionally identical devices can be related to the device's power consumption.

Nichols, D. K.↗
NASA NTRS1990

Forward Bias Inhibits Single-Event Upsets

Bipolar integrated circuits more resistant to ionizing radiation. Tests show resistance of bipolar integrated logic or memory circuit by single-event upsets increased by imparting forward bias to diode constituted by buried layer of substrate and collector.

Zoutendyk, John A.↗
NASA NTRS1980

A study of single event upsets in static RAM's

Several types of CMOS static random access memories (RAMs) have been tested in a cyclotron for susceptibility to single event upsets and latchup such as might occur in earth orbit or interplanetary space. No upsets have been observed for neutron fluences of 10 to the 11th n/sq cm and higher or proton fluences of 10 to the 9th protons/sq cm.

Price, W. E.↗
NASA NTRS1991

Heavy-ion induced single-event upset in integrated circuits

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Zoutendyk, J. A.↗
NASA NTRS1993

Modeling and experimental verification of single event upsets

The research performed and the results obtained at the Laboratory for Radiation Studies, Prairie View A&M University and Texas A&I University, on the problem of Single Events Upsets, the various schemes employed to limit them and the effects they have on the reliability and fault tolerance at the systems level, such as robotic systems are reviewed.

Fogarty, T. N.↗