Engineering topics
Publications and source records attributed to Zoutendyk, John A..
Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.
Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.
Two reports describe preliminary theoretical and experimental studies based on method described in "Laser Scanner Tests For Single-Event Upsets" (NPO-18216). Laser-scan and heavy-ion data found correlated within factor of two. Method of testing for single-event upsets intended to overcome disadvantages of, complement, and/or substitute for more-expensive cyclotron-testing method, which does not provide spatial resolution.
Report presents results of experiments where multiple-bit errors were induced in 256-kbit commercial integrated-circuit dynamic random-access memory (DRAM) by variety of normally incident heavy ions. Idea demonstrates utility of DRAM and methods used to analyze experimental data, with view towards applying methods and data to other digital integrated circuits.
Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.
Report describes experimental and computer-simulation study of multiple-bit errors caused by impingement of single energetic ions on 256-Kb dynamic random-access memory (DRAM) integrated circuit. Studies illustrate effects of different mechanisms for transport of charge from ion tracks to various elements of integrated circuits. Shows multiple-bit errors occur in two different types of clusters about ion tracks causing them.
Bipolar integrated circuits more resistant to ionizing radiation. Tests show resistance of bipolar integrated logic or memory circuit by single-event upsets increased by imparting forward bias to diode constituted by buried layer of substrate and collector.
Collection of mathematical models includes second-order effects in n-channel, enhancement-mode, metal-oxide-semiconductor field-effect transistors (MOSFET's). When dimensions of circuit elements relatively large, effects neglected safely. However, as very-large-scale integration of microelectronic circuits leads to MOSFET's shorter or narrower than 2 micrometer, effects become significant in design and operation. Such computer programs as widely-used "Simulation Program With Integrated Circuit Emphasis, Version 2" (SPICE 2) include many of these effects. In second-order models of n-channel, enhancement-mode MOSFET, first-order gate-depletion region diminished by triangular-cross-section deletions on end and augmented by circular-wedge-cross-section bulges on sides.
Error-correcting Hamming code built into circuit. A 256 K dynamic random-access memory (DRAM) circuit incorporates Hamming error-correcting code in its layout. Feature provides faster detection and correction of errors at less cost in amount of equipment, operating time, and software. On-chip error-correcting feature also makes new DRAM less susceptible to single-event upsets.
Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.
Report describes measurements of common-emitter current gains (hFE) of advanced bipolar silicon transistors before, during, and after irradiation with 275-MeV bromine ions, 2.5-MeV electrons, and conductivity rays from cobalt-60 atoms.
Single-event upsets (SEU's) propagate to adjacent cells in integrated memory circuits. Findings of experiments in lateral transport of electrical-charge carriers from ion tracks in 256K dynamic randon-access memories (DRAM's). As dimensions of integrated circuits decrease, vulnerability to SEU's increases. Understanding gained enables design of less vulnerable circuits.
Theoretical paper discusses response of enhancement-mode metal oxide/semiconductor field-effect transistor to cosmic-ray ion that passes perpendicularly through gate-oxide layers. Even if ion causes no permanent damage, temporary increase of electrical conductivity along track of ion large enough and long enough to cause change in logic state in logic circuit containing MOSFET.
Experimental study presents examples of empirical modeling of single-event upset in negatively-doped-source/drain metal-oxide-semiconductor static random-access memory cells. Data supports adoption of simplified worst-case model in which cross sectionof SEU by ion above threshold energy equals area of memory cell.
Report presents theory and experimental data regarding newly discovered mode for single-event upsets, (SEU's) in complementary metal-oxide/semiconductor, static random-access memories, CMOS SRAM's. SEU cross sections larger than those expected from previously known modes given rise to speculation regarding additional mode, and subsequent cross-section measurements appear to confirm speculation.
Experimental measurements are reported of the degradation effects of high-energy particles (heavy Br ions and electrons) and Co-60 gamma-rays on the current gain of minimum-geometry bipolar transistors made from an advanced process. The data clearly illustrate the total-ionizing-dose vs particle-fluence behavior of this bipolar transistor produced by an advanced process. In particular, bulk damage from Co-60 gamma rays in bipolar transistors (base transport factor degradation) and surface damage in bipolar transistors from ionizing radiation (emitter-efficiency degradation) have been observed. The true equivalence between various types of radiation for this process technology has been determined on the basis of damage from the log K1 intercepts.
An extensive analytical and experimental study SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes.
Mathematical model yields estimates of upper and lower bounds on rates of single-event upsets (SEU's) in logic circuits. SEU's are reversible changes in logic states, caused by single high-energy ions. Energetic ions passed through device along tracks perpendicular to surface, to determine parameters of model. Used to estimate rates caused by ions of various energies incident at arbitrary angles. Useful in design of integrated circuits as high-density memories for minimal susceptibility to bit errors.