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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3

Two-dimensional perovskite heterostructures for single crystal semiconductor devices

Two-dimensional (2D) perovskites have gained much attention lately owing to their excellent optoelectronic properties, chemical tunability, and environmental stability. Multiple methods have been devised to synthesize high quality 2D perovskite single crystals, and recent progress in fabricating its heterostructures is notable as well. In particular, with growing interest in 2D van der Waals heterostructures, 2D perovskites have become a strong candidate as a new building block for heterostructures to reveal unique physical properties across different interfaces. Until now, various heterostructure devices of 2D perovskite single crystals with other types of 2D materials such as transition metal dichalcogenides (TMDs) and graphene have been studied, which have shown intriguing results including interlayer excitons and enhanced electronic properties. Here, we introduce various synthetic approaches to realize 2D perovskite single crystals and unique characteristics of their single crystal heterostructures fabricated with precision, possessing sharp interfaces. Moreover, recent studies of semiconductor devices based on 2D perovskite single crystal heterostructures are discussed in-depth. New perspectives to further the horizon in the field of 2D perovskite heterostructures are suggested in this work including the consideration of metal–2D material van der Waals contact, application of dry transfer techniques, electric bias driven ion diffusion studies, and nanocrystal array fabrication. 2D perovskite heterostructure single crystal devices factoring in these novel perspectives will further uncover the true potential of these materials for highly efficient and stable semiconductor devices.

Physics↗

Strategies for Radiation Hardness Testing of Power Semiconductor Devices

Plans on the drawing board for future space missions call for much larger power systems than have been flown in the past. These systems would employ much higher voltages and currents to enable more powerful electric propulsion engines and other improvements on what will also be much larger spacecraft. Long term human outposts on the moon and planets would also require high voltage, high current and long life power sources. Only hundreds of watts are produced and controlled on a typical robotic exploration spacecraft today. Megawatt systems are required for tomorrow. Semiconductor devices used to control and convert electrical energy in large space power systems will be exposed to electromagnetic and particle radiation of many types, depending on the trajectory and duration of the mission and on the power source. It is necessary to understand the often very different effects of the radiations on the control and conversion systems. Power semiconductor test strategies that we have developed and employed will be presented, along with selected results. The early results that we have obtained in testing large power semiconductor devices give a good indication of the degradation in electrical performance that can be expected in response to a given dose. We are also able to highlight differences in radiation hardness that may be device or material specific.

Soltis, James V.↗

Multilevel metallization method for fabricating a metal oxide semiconductor device

An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

Hollis, B. R., Jr.↗

Interconnection of Semiconductor Devices in Extreme Environment Microelectronic Integrated Circuit Chips

A process of fabrication and the resulting integrated circuit device is made of patterned metal electrical interconnections between semiconductor devices residing on and forming extremely harsh environment integrated circuit chips. The process enables more complicated wide band gap semiconductor integrated circuits with more than one level of interconnect to function for prolonged time periods (over 1000 hours) at much higher temperatures (500 C).

Spry, David J.↗

Radiation-Hardness Data For Semiconductor Devices

Document presents data on and analysis of radiation hardness of various semiconductor devices. Data specifies total-dose radiation tolerance of devices. Volume 1 of report covers diodes, bipolar transistors, field effect transistors, silicon controlled rectifiers and optical devices. Volume 2 covers integrated circuits. Volume 3 provides detailed analysis of data in volumes 1 and 2.

Price, W. E.↗

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Powell, J. Anthony↗

Comparison of Non-Parabolic Hydrodynamic Simulations for Semiconductor Devices

Parabolic drift-diffusion simulators are common engineering level design tools for semiconductor devices. Hydrodynamic simulators, based on the parabolic band approximation, are becoming more prevalent as device dimensions shrink and energy transport effects begin to dominate device characteristic. However, band structure effects present in state-of-the-art devices necessitate relaxing the parabolic band approximation. This paper presents simulations of ballistic diodes, a benchmark device, of Si and GaAs using two different non-parabolic hydrodynamic formulations. The first formulation uses the Kane dispersion relationship in the derivation of the conservation equations. The second model uses a power law dispersion relation {(hk)(exp 2)/2m = xW(exp Y)}. Current-voltage relations show that for the ballistic diodes considered. the non-parabolic formulations predict less current than the parabolic case. Explanations of this will be provided by examination of velocity and energy profiles. At low bias, the simulations based on the Kane formulation predict greater current flow than the power law formulation. As the bias is increased this trend changes and the power law predicts greater current than the Kane formulation. It will be shown that the non-parabolicity and energy range of the hydrodynamic model based on the Kane dispersion relation are limited due to the binomial approximation which was utilized in the derivation.

Smith, A. W.↗

Glass encapsulation provides extra protection for IC semiconductor devices

Oxide-passivated semiconductor chip is given protective glass coating by means of vapor deposition over metallic substrate of integrated circuit (IC). Method provides more reliable oxide-passivation and hermetic sealing in current use. Chips and scratches incurred during dicing, testing, and assembly are markedly reduced.

Doelp, W. L., Jr.↗

Better Ohmic Contacts For InP Semiconductor Devices

Four design modifications enable fabrication of improved ohmic contacts on InP-based semiconductor devices. First modification consists of insertion of layer of gold phosphide between n-doped InP and metal or other overlayer of contact material. Second, includes first modification plus use of particular metal overlayer to achieve very low contact resistivities. Third, also involves deposition of Au(2)P(3) interlayer; in addition, refractory metal (W or Ta) deposited to form contact overlayer. In fourth, contact layer of Auln alloy deposited directly on InP. Improved contacts exhibit low electrical resistances and fabricated without exposing devices to destructive predeposition or postdeposition treatments.

Weizer, Victor G.↗

Wide Bandgap Semiconductor Devices and Systems for Communications in Extreme Environment

The feasibility of gallium nitride based wide bandgap semiconductor devices for signal amplification in extreme planetary environment is investigated. The measured performance of these devices at S-band, X-band, and Ka-band are presented. The data indicates excellent performance at the above frequencies. Potential application of these devices includes communication systems required to operate in the extreme hot environment of Venus and in the extreme cold and high radiation environment of Jupiter’s icy moons.

Gallium Nitride↗

Improvement of screening methods for silicon planar semiconductor devices

The results of the program for the development of a more sensitive method for selecting silicon planar semiconductor devices for long life applications are reported. The manufacturing technologies (MOS and Bipolar) are discussed along with the screening procedures developed as a result of the tests and evaluations, and the effectiveness of the MOS and Bilayer screening procedures are evaluated.

Berger, W. M.↗

Ti/Pd/Cu Contacts for Semiconductor Devices

Copper systems equivalent in performance to silver or gold systems. Titanium layer and palladium layer deposited on semiconductor device by electron beam evaporation. Desired pattern etched using photoresist. Thin layer of copper plated on contact pattern from cyanide solution. Copper layer then built up to 4 to 8 microns by electroplatng from acid solution.

Campbell, R. B.↗